2 files changed, 52 insertions, 13 deletions

diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 5378ec89e..86d654cc4 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -118,7 +118,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
 	return true;
 }
 
-static void detect_fsm(RTLIL::Wire *wire)
+static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
 {
 	bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
 	bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
@@ -199,7 +199,7 @@ static void detect_fsm(RTLIL::Wire *wire)
 		}
 
 		SigSpec sig_y = sig_d, sig_undef;
-		if (ce.eval(sig_y, sig_undef))
+		if (!ignore_self_reset && ce.eval(sig_y, sig_undef))
 			is_self_resetting = true;
 	}
 
@@ -261,12 +261,15 @@ struct FsmDetectPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    fsm_detect [selection]\n");
+		log("    fsm_detect [options] [selection]\n");
 		log("\n");
 		log("This pass detects finite state machines by identifying the state signal.\n");
 		log("The state signal is then marked by setting the attribute 'fsm_encoding'\n");
 		log("on the state signal to \"auto\".\n");
 		log("\n");
+		log("    -ignore-self-reset\n");
+		log("        Mark FSMs even if they are self-resetting\n");
+		log("\n");
 		log("Existing 'fsm_encoding' attributes are not changed by this pass.\n");
 		log("\n");
 		log("Signals can be protected from being detected by this pass by setting the\n");
@@ -276,16 +279,28 @@ struct FsmDetectPass : public Pass {
 		log("before this pass to prepare the design for fsm_detect.\n");
 		log("\n");
 #ifdef YOSYS_ENABLE_VERIFIC
-		log("The Verific frontend may merge multiplexers in a way that interferes with FSM\n");
+		log("The Verific frontend may optimize the design in a way that interferes with FSM\n");
 		log("detection. Run 'verific -cfg db_infer_wide_muxes_post_elaboration 0' before\n");
-		log("reading the source, and 'bmuxmap' after 'proc' for best results.\n");
+		log("reading the source, and 'bmuxmap -pmux' after 'proc' for best results.\n");
 		log("\n");
 #endif
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
-		extra_args(args, 1, design);
+
+		bool ignore_self_reset = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-ignore-self-reset") {
+				ignore_self_reset = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
 
 		CellTypes ct;
 		ct.setup_internals();
@@ -321,7 +336,7 @@ struct FsmDetectPass : public Pass {
 					sig_at_port.add(assign_map(wire));
 
 			for (auto wire : module->selected_wires())
-				detect_fsm(wire);
+				detect_fsm(wire, ignore_self_reset);
 		}
 
 		assign_map.clear();
diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc
index 03673c278..15b149239 100644
--- a/passes/techmap/bmuxmap.cc
+++ b/passes/techmap/bmuxmap.cc
@@ -36,10 +36,16 @@ struct BmuxmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		bool pmux_mode = false;
+
 		log_header(design, "Executing BMUXMAP pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-pmux") {
+				pmux_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -53,18 +59,36 @@ struct BmuxmapPass : public Pass {
 			SigSpec sel = cell->getPort(ID::S);
 			SigSpec data = cell->getPort(ID::A);
 			int width = GetSize(cell->getPort(ID::Y));
+			int s_width = GetSize(cell->getPort(ID::S));
 
-			for (int idx = 0; idx < GetSize(sel); idx++) {
-				SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
-				for (int i = 0; i < GetSize(new_data); i += width) {
-					RTLIL::Cell *mux = module->addMux(NEW_ID,
+			if(pmux_mode)
+			{
+				int num_cases = 1 << s_width;
+				SigSpec new_a = SigSpec(State::Sx, width);
+				SigSpec new_s = module->addWire(NEW_ID, num_cases);
+				SigSpec new_data = module->addWire(NEW_ID, width);
+				for (int val = 0; val < num_cases; val++)
+				{
+					module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
+				}
+				RTLIL::Cell *pmux = module->addPmux(NEW_ID, new_a, data, new_s, new_data);
+				pmux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+				data = new_data;
+			}
+			else
+			{
+				for (int idx = 0; idx < GetSize(sel); idx++) {
+					SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
+					for (int i = 0; i < GetSize(new_data); i += width) {
+						RTLIL::Cell *mux = module->addMux(NEW_ID,
 							data.extract(i*2, width),
 							data.extract(i*2+width, width),
 							sel[idx],
 							new_data.extract(i, width));
-					mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+						mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
+					}
+					data = new_data;
 				}
-				data = new_data;
 			}
 
 			module->connect(cell->getPort(ID::Y), data);