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-rw-r--r--passes/techmap/abc9.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index f90834aa9..0312e3e1f 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -124,6 +124,7 @@ void handle_loops(RTLIL::Design *design)
RTLIL::SigSpec sig;
for (auto b : it->second) {
Wire *w = b.wire;
+ if (!w) continue;
if (w->port_output) {
log_assert(w->get_bool_attribute("\\abc_scc_break"));
w = module->wire(stringf("%s.abci", w->name.c_str()));