diff options
Diffstat (limited to 'passes')
-rw-r--r-- | passes/cmds/edgetypes.cc | 6 | ||||
-rw-r--r-- | passes/cmds/plugin.cc | 2 | ||||
-rw-r--r-- | passes/cmds/qwp.cc | 20 | ||||
-rw-r--r-- | passes/cmds/scc.cc | 4 | ||||
-rw-r--r-- | passes/cmds/splitnets.cc | 4 | ||||
-rw-r--r-- | passes/cmds/stat.cc | 2 | ||||
-rw-r--r-- | passes/equiv/equiv_add.cc | 2 | ||||
-rw-r--r-- | passes/fsm/fsmdata.h | 2 | ||||
-rw-r--r-- | passes/hierarchy/hierarchy.cc | 10 | ||||
-rw-r--r-- | passes/memory/memory_bram.cc | 10 | ||||
-rw-r--r-- | passes/memory/memory_collect.cc | 2 | ||||
-rw-r--r-- | passes/memory/memory_share.cc | 2 | ||||
-rw-r--r-- | passes/opt/opt_const.cc | 2 | ||||
-rw-r--r-- | passes/opt/share.cc | 58 | ||||
-rw-r--r-- | passes/opt/wreduce.cc | 6 | ||||
-rw-r--r-- | passes/sat/eval.cc | 2 | ||||
-rw-r--r-- | passes/sat/freduce.cc | 2 | ||||
-rw-r--r-- | passes/sat/sat.cc | 12 | ||||
-rw-r--r-- | passes/techmap/abc.cc | 2 | ||||
-rw-r--r-- | passes/techmap/alumacc.cc | 6 | ||||
-rw-r--r-- | passes/techmap/dffinit.cc | 4 | ||||
-rw-r--r-- | passes/techmap/extract.cc | 2 | ||||
-rw-r--r-- | passes/techmap/maccmap.cc | 2 | ||||
-rw-r--r-- | passes/techmap/muxcover.cc | 6 | ||||
-rw-r--r-- | passes/techmap/simplemap.cc | 2 | ||||
-rw-r--r-- | passes/tests/test_cell.cc | 2 |
26 files changed, 87 insertions, 87 deletions
diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 5f062c6e8..7b75a009f 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -52,7 +52,7 @@ struct EdgetypePass : public Pass { for (auto module : design->selected_modules()) { SigMap sigmap(module); - dict<SigBit, pool<std::tuple<IdString, IdString, int>>> bit_sources, bit_sinks; + dict<SigBit, pool<tuple<IdString, IdString, int>>> bit_sources, bit_sinks; pool<std::pair<IdString, IdString>> multibit_ports; for (auto cell : module->selected_cells()) @@ -67,9 +67,9 @@ struct EdgetypePass : public Pass { for (int i = 0; i < GetSize(sig); i++) { if (cell->output(port_name)) - bit_sources[sig[i]].insert(std::tuple<IdString, IdString, int>(cell_type, port_name, i)); + bit_sources[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i)); if (cell->input(port_name)) - bit_sinks[sig[i]].insert(std::tuple<IdString, IdString, int>(cell_type, port_name, i)); + bit_sinks[sig[i]].insert(tuple<IdString, IdString, int>(cell_type, port_name, i)); } } diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index f7c65bbde..e2d80d9bf 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -115,7 +115,7 @@ struct PluginPass : public Pass { log("\n"); int max_alias_len = 1; for (auto &it : loaded_plugin_aliases) - max_alias_len = std::max(max_alias_len, GetSize(it.first)); + max_alias_len = max(max_alias_len, GetSize(it.first)); for (auto &it : loaded_plugin_aliases) log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str()); } diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc index 784076c37..8ec815a72 100644 --- a/passes/cmds/qwp.cc +++ b/passes/cmds/qwp.cc @@ -342,8 +342,8 @@ struct QwpWorker double r = alt_mode ? alt_radius : radius; if (std::isfinite(v)) { - v = std::min(v, c+r); - v = std::max(v, c-r); + v = min(v, c+r); + v = max(v, c-r); } else { v = c; } @@ -524,15 +524,15 @@ struct QwpWorker if (rel_pos < 0) { node.pos = midpos + left_scale*rel_pos; if (std::isfinite(node.pos)) { - node.pos = std::min(node.pos, midpos); - node.pos = std::max(node.pos, midpos - radius); + node.pos = min(node.pos, midpos); + node.pos = max(node.pos, midpos - radius); } else node.pos = midpos - radius/2; } else { node.pos = midpos + right_scale*rel_pos; if (std::isfinite(node.pos)) { - node.pos = std::max(node.pos, midpos); - node.pos = std::min(node.pos, midpos + radius); + node.pos = max(node.pos, midpos); + node.pos = min(node.pos, midpos + radius); } else node.pos = midpos + radius/2; } @@ -666,8 +666,8 @@ struct QwpWorker double max_value = values.front(); for (auto &v : values) { - min_value = std::min(min_value, v); - max_value = std::max(max_value, v); + min_value = min(min_value, v); + max_value = max(max_value, v); } if (fabs(max_value - min_value) < 0.001) { @@ -679,8 +679,8 @@ struct QwpWorker int max_bucket_val = 0; for (auto &v : values) { - int idx = std::min(int(GetSize(buckets) * (v - min_value) / (max_value - min_value)), GetSize(buckets)-1); - max_bucket_val = std::max(max_bucket_val, ++buckets.at(idx)); + int idx = min(int(GetSize(buckets) * (v - min_value) / (max_value - min_value)), GetSize(buckets)-1); + max_bucket_val = max(max_bucket_val, ++buckets.at(idx)); } for (int i = 4; i >= 0; i--) { diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 43a43b4fc..532026f26 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -69,10 +69,10 @@ struct SccWorker for (auto nextCell : cellToNextCell[cell]) if (cellLabels.count(nextCell) == 0) { run(nextCell, depth+1, maxDepth); - cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second); + cellLabels[cell].second = min(cellLabels[cell].second, cellLabels[nextCell].second); } else if (cellsOnStack.count(nextCell) > 0 && (maxDepth < 0 || cellDepth[nextCell] + maxDepth > depth)) { - cellLabels[cell].second = std::min(cellLabels[cell].second, cellLabels[nextCell].second); + cellLabels[cell].second = min(cellLabels[cell].second, cellLabels[nextCell].second); } if (cellLabels[cell].first == cellLabels[cell].second) diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 3b6ad014f..a64c48791 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -140,8 +140,8 @@ struct SplitnetsPass : public Pass { for (auto wire : module->wires()) if (wire->port_id != 0) { - normalized_port_factor = std::max(normalized_port_factor, wire->port_id+1); - normalized_port_factor = std::max(normalized_port_factor, GetSize(wire)+1); + normalized_port_factor = max(normalized_port_factor, wire->port_id+1); + normalized_port_factor = max(normalized_port_factor, GetSize(wire)+1); } for (auto wire : module->wires()) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index ed4a04064..af56a9e20 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -110,7 +110,7 @@ struct statdata_t int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0; int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0; int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0; - cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y})); + cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y})); } else if (cell_type.in("$mux", "$pmux")) cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y"))); diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 7b8ba9058..9ae490fe7 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -63,7 +63,7 @@ struct EquivAddPass : public Pass { auto port = conn.first; SigSpec gold_sig = gold_cell->getPort(port); SigSpec gate_sig = gate_cell->getPort(port); - int width = std::min(GetSize(gold_sig), GetSize(gate_sig)); + int width = min(GetSize(gold_sig), GetSize(gate_sig)); if (gold_cell->input(port) && gate_cell->input(port)) { diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h index 1b98ccbac..68222769a 100644 --- a/passes/fsm/fsmdata.h +++ b/passes/fsm/fsmdata.h @@ -39,7 +39,7 @@ struct FsmData int state_num_log2 = 0; for (int i = state_table.size(); i > 0; i = i >> 1) state_num_log2++; - state_num_log2 = std::max(state_num_log2, 1); + state_num_log2 = max(state_num_log2, 1); cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits); cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size()); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 598fe9396..fcc30d175 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -66,7 +66,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, for (auto &conn : i2.second->connections()) { if (conn.first[0] != '$') portnames.insert(conn.first); - portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.size()); + portwidths[conn.first] = max(portwidths[conn.first], conn.second.size()); } for (auto ¶ : i2.second->parameters) parameters.insert(para.first); @@ -84,8 +84,8 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, for (auto &decl : portdecls) if (decl.index > 0) { - portwidths[decl.portname] = std::max(portwidths[decl.portname], 1); - portwidths[decl.portname] = std::max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]); + portwidths[decl.portname] = max(portwidths[decl.portname], 1); + portwidths[decl.portname] = max(portwidths[decl.portname], portwidths[stringf("$%d", decl.index)]); log(" port %d: %s [%d:0] %s\n", decl.index, decl.input ? decl.output ? "inout" : "input" : "output", portwidths[decl.portname]-1, RTLIL::id2cstr(decl.portname)); if (indices.count(decl.index) > ports.size()) log_error("Port index (%d) exceeds number of found ports (%d).\n", decl.index, int(ports.size())); @@ -106,7 +106,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, log_assert(!indices.empty()); indices.erase(d.index); ports[d.index-1] = d; - portwidths[d.portname] = std::max(portwidths[d.portname], 1); + portwidths[d.portname] = max(portwidths[d.portname], 1); log(" port %d: %s [%d:0] %s\n", d.index, d.input ? d.output ? "inout" : "input" : "output", portwidths[d.portname]-1, RTLIL::id2cstr(d.portname)); goto found_matching_decl; } @@ -327,7 +327,7 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db) db[module] = 0; for (auto cell : module->cells()) if (design->module(cell->type)) - db[module] = std::max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1); + db[module] = max(db[module], find_top_mod_score(design, design->module(cell->type), db) + 1); } return db.at(module); } diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index b371578d4..f2d9b5847 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -387,9 +387,9 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, if (pi.clkpol > 1) clkpol_wr_ports.insert(pi.clkpol); } - clocks_max = std::max(clocks_max, pi.clocks); - clkpol_max = std::max(clkpol_max, pi.clkpol); - transp_max = std::max(transp_max, pi.transp); + clocks_max = max(clocks_max, pi.clocks); + clkpol_max = max(clkpol_max, pi.clkpol); + transp_max = max(transp_max, pi.transp); } log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant); @@ -977,7 +977,7 @@ void handle_cell(Cell *cell, const rules_t &rules) log("\n"); pool<pair<IdString, int>> failed_brams; - dict<pair<int, int>, std::tuple<int, int, int>> best_rule_cache; + dict<pair<int, int>, tuple<int, int, int>> best_rule_cache; for (int i = 0; i < GetSize(rules.matches); i++) { @@ -1078,7 +1078,7 @@ void handle_cell(Cell *cell, const rules_t &rules) } log(" Storing for later selection.\n"); - best_rule_cache[pair<int, int>(i, vi)] = std::tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]); + best_rule_cache[pair<int, int>(i, vi)] = tuple<int, int, int>(match_properties["efficiency"], -match_properties["cells"], -match_properties["acells"]); next_match_rule: if (or_next_if_better || best_rule_cache.empty()) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index abd4b1242..5c0acb3e5 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -64,7 +64,7 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) for (auto &cell_it : module->cells_) { Cell *cell = cell_it.second; if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) { - addr_bits = std::max(addr_bits, cell->getParam("\\ABITS").as_int()); + addr_bits = max(addr_bits, cell->getParam("\\ABITS").as_int()); memcells.push_back(cell); } } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b8f27025a..3a6fd0b44 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -210,7 +210,7 @@ struct MemoryShareWorker if (non_feedback_nets.count(sig_data[i])) goto not_pure_feedback_port; - async_rd_bits[sig_addr].resize(std::max(async_rd_bits.size(), sig_data.size())); + async_rd_bits[sig_addr].resize(max(async_rd_bits.size(), sig_data.size())); for (int i = 0; i < int(sig_data.size()); i++) async_rd_bits[sig_addr][i].insert(sig_data[i]); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 85e4c4c18..0fcacf0a8 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -589,7 +589,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec b = cell->getPort("\\B"); if (cell->parameters["\\A_WIDTH"].as_int() != cell->parameters["\\B_WIDTH"].as_int()) { - int width = std::max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); + int width = max(cell->parameters["\\A_WIDTH"].as_int(), cell->parameters["\\B_WIDTH"].as_int()); a.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()); b.extend_u0(width, cell->parameters["\\A_SIGNED"].as_bool() && cell->parameters["\\B_SIGNED"].as_bool()); } diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 9dd0dc0a3..1d9b1006e 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -113,8 +113,8 @@ struct ShareWorker static int bits_macc_port(const Macc::port_t &p, int width) { if (GetSize(p.in_a) == 0 || GetSize(p.in_b) == 0) - return std::min(std::max(GetSize(p.in_a), GetSize(p.in_b)), width); - return std::min(GetSize(p.in_a), width) * std::min(GetSize(p.in_b), width) / 2; + return min(max(GetSize(p.in_a), GetSize(p.in_b)), width); + return min(GetSize(p.in_a), width) * min(GetSize(p.in_b), width) / 2; } static int bits_macc(const Macc &m, int width) @@ -224,13 +224,13 @@ struct ShareWorker supermacc->ports.push_back(p); } - int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * std::max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1); + int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1); - for (int i = 0; i < std::min(GetSize(p1.in_a), GetSize(p2.in_a)); i++) + for (int i = 0; i < min(GetSize(p1.in_a), GetSize(p2.in_a)); i++) if (p1.in_a[i] == p2.in_a[i] && score > 0) score--; - for (int i = 0; i < std::min(GetSize(p1.in_b), GetSize(p2.in_b)); i++) + for (int i = 0; i < min(GetSize(p1.in_b), GetSize(p2.in_b)); i++) if (p1.in_b[i] == p2.in_b[i] && score > 0) score--; @@ -243,7 +243,7 @@ struct ShareWorker Macc m1(c1), m2(c2), supermacc; int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y")); - int width = std::max(w1, w2); + int width = max(w1, w2); m1.optimize(w1); m2.optimize(w2); @@ -419,8 +419,8 @@ struct ShareWorker int a2_width = c2->parameters.at("\\A_WIDTH").as_int(); int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); - if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; - if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false; + if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false; } return true; @@ -438,9 +438,9 @@ struct ShareWorker int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); - if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false; - if (std::max(b1_width, b2_width) > 2 * std::min(b1_width, b2_width)) return false; - if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false; + if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false; + if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false; } return true; @@ -458,15 +458,15 @@ struct ShareWorker int b2_width = c2->parameters.at("\\B_WIDTH").as_int(); int y2_width = c2->parameters.at("\\Y_WIDTH").as_int(); - int min1_width = std::min(a1_width, b1_width); - int max1_width = std::max(a1_width, b1_width); + int min1_width = min(a1_width, b1_width); + int max1_width = max(a1_width, b1_width); - int min2_width = std::min(a2_width, b2_width); - int max2_width = std::max(a2_width, b2_width); + int min2_width = min(a2_width, b2_width); + int max2_width = max(a2_width, b2_width); - if (std::max(min1_width, min2_width) > 2 * std::min(min1_width, min2_width)) return false; - if (std::max(max1_width, max2_width) > 2 * std::min(max1_width, max2_width)) return false; - if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false; + if (max(min1_width, min2_width) > 2 * min(min1_width, min2_width)) return false; + if (max(max1_width, max2_width) > 2 * min(max1_width, max2_width)) return false; + if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false; } return true; @@ -475,7 +475,7 @@ struct ShareWorker if (c1->type == "$macc") { if (!config.opt_aggressive) - if (share_macc(c1, c2) > 2 * std::min(bits_macc(c1), bits_macc(c2))) return false; + if (share_macc(c1, c2) > 2 * min(bits_macc(c1), bits_macc(c2))) return false; return true; } @@ -532,8 +532,8 @@ struct ShareWorker RTLIL::SigSpec a2 = c2->getPort("\\A"); RTLIL::SigSpec y2 = c2->getPort("\\Y"); - int a_width = std::max(a1.size(), a2.size()); - int y_width = std::max(y1.size(), y2.size()); + int a_width = max(a1.size(), a2.size()); + int y_width = max(y1.size(), y2.size()); a1.extend_u0(a_width, a_signed); a2.extend_u0(a_width, a_signed); @@ -563,11 +563,11 @@ struct ShareWorker if (config.generic_cbin_ops.count(c1->type)) { - int score_unflipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) + - std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()); + int score_unflipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) + + max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()); - int score_flipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) + - std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()); + int score_flipped = max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) + + max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()); if (score_flipped < score_unflipped) { @@ -630,13 +630,13 @@ struct ShareWorker RTLIL::SigSpec b2 = c2->getPort("\\B"); RTLIL::SigSpec y2 = c2->getPort("\\Y"); - int a_width = std::max(a1.size(), a2.size()); - int b_width = std::max(b1.size(), b2.size()); - int y_width = std::max(y1.size(), y2.size()); + int a_width = max(a1.size(), a2.size()); + int b_width = max(b1.size(), b2.size()); + int y_width = max(y1.size(), y2.size()); if (c1->type == "$shr" && a_signed) { - a_width = std::max(y_width, a_width); + a_width = max(y_width, a_width); if (a1.size() < y1.size()) a1.extend_u0(y1.size(), true); if (a2.size() < y2.size()) a2.extend_u0(y2.size(), true); diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index e2d9a2c4f..df416e4c5 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -188,8 +188,8 @@ struct WreduceWorker int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1; if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { - max_port_a_size = std::min(max_port_a_size, GetSize(sig)); - max_port_b_size = std::min(max_port_b_size, GetSize(sig)); + max_port_a_size = min(max_port_a_size, GetSize(sig)); + max_port_b_size = min(max_port_b_size, GetSize(sig)); } bool port_a_signed = false; @@ -228,7 +228,7 @@ struct WreduceWorker if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A")); if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B")); - int max_y_size = std::max(a_size, b_size); + int max_y_size = max(a_size, b_size); if (cell->type == "$add") max_y_size++; diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 522664032..614a1bd31 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -568,7 +568,7 @@ struct EvalPass : public Pass { if (tab_column_width.size() < row.size()) tab_column_width.resize(row.size()); for (size_t i = 0; i < row.size(); i++) - tab_column_width[i] = std::max(tab_column_width[i], int(row[i].size())); + tab_column_width[i] = max(tab_column_width[i], int(row[i].size())); } log("\n"); diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index e0d11243b..373b80488 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -265,7 +265,7 @@ struct PerformReduction } int max_child_depth = 0; for (auto &bit : drv.second) - max_child_depth = std::max(register_cone_worker(celldone, sigdepth, bit), max_child_depth); + max_child_depth = max(register_cone_worker(celldone, sigdepth, bit), max_child_depth); sigdepth[out] = max_child_depth + 1; } else { pi_bits.push_back(out); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index e72eddf33..2e9c6d2f9 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -606,8 +606,8 @@ struct SatHelper int maxModelWidth = 10; for (auto &info : modelInfo) { - maxModelName = std::max(maxModelName, int(info.description.size())); - maxModelWidth = std::max(maxModelWidth, info.width); + maxModelName = max(maxModelName, int(info.description.size())); + maxModelWidth = max(maxModelWidth, info.width); } log("\n"); @@ -781,9 +781,9 @@ struct SatHelper wavedata[info.description].first = info.width; wavedata[info.description].second[info.timestep] = value; - mintime = std::min(mintime, info.timestep); - maxtime = std::max(maxtime, info.timestep); - maxwidth = std::max(maxwidth, info.width); + mintime = min(mintime, info.timestep); + maxtime = max(maxtime, info.timestep); + maxwidth = max(maxwidth, info.width); } fprintf(f, "{ \"signal\": ["); @@ -1116,7 +1116,7 @@ struct SatPass : public Pass { continue; } if (args[argidx] == "-stepsize" && argidx+1 < args.size()) { - stepsize = std::max(1, atoi(args[++argidx].c_str())); + stepsize = max(1, atoi(args[++argidx].c_str())); continue; } if (args[argidx] == "-ignore_div_by_zero") { diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index 645869273..706779885 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1399,7 +1399,7 @@ struct AbcPass : public Pass { std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up; std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down; - typedef std::tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t; + typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t; std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells; std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse; diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 90563c863..3c7ff4b92 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -40,7 +40,7 @@ struct AlumaccWorker { std::vector<RTLIL::Cell*> cells; RTLIL::SigSpec a, b, c, y; - std::vector<std::tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp; + std::vector<tuple<bool, bool, bool, bool, RTLIL::SigSpec>> cmp; bool is_signed, invert_b; RTLIL::Cell *alu_cell; @@ -138,7 +138,7 @@ struct AlumaccWorker n->users = 0; for (auto bit : n->y) - n->users = std::max(n->users, bit_users.at(bit) - 1); + n->users = max(n->users, bit_users.at(bit) - 1); if (cell->type.in("$pos", "$neg")) { @@ -409,7 +409,7 @@ struct AlumaccWorker n->a = A; n->b = B; n->c = RTLIL::S1; - n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B))); + n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B))); n->is_signed = is_signed; n->invert_b = true; sig_alu[RTLIL::SigSig(A, B)].insert(n); diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 84770ff3e..6a80f043b 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -68,7 +68,7 @@ struct DffinitPass : public Pass { for (auto wire : module->selected_wires()) { if (wire->attributes.count("\\init")) { Const value = wire->attributes.at("\\init"); - for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) + for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) init_bits[sigmap(SigBit(wire, i))] = value[i]; } if (wire->port_output) @@ -116,7 +116,7 @@ struct DffinitPass : public Pass { if (wire->attributes.count("\\init")) { Const &value = wire->attributes.at("\\init"); bool do_cleanup = true; - for (int i = 0; i < std::min(GetSize(value), GetSize(wire)); i++) { + for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) { SigBit bit = sigmap(SigBit(wire, i)); if (cleanup_bits.count(bit) || !used_bits.count(bit)) value[i] = State::Sx; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index d9ec4bc6a..fc73177ce 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -130,7 +130,7 @@ public: RTLIL::SigSpec needleSig = conn.second; RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str())); - for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) { + for (int i = 0; i < min(needleSig.size(), haystackSig.size()); i++) { RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire; if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire) if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr)) diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index dad1c06ac..d5b8fe804 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -134,7 +134,7 @@ struct MaccmapWorker } return retval; #else - return std::max(n - 1, 0); + return max(n - 1, 0); #endif } diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index b250c5680..514c3365f 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -49,8 +49,8 @@ struct MuxcoverWorker vector<tree_t> tree_list; - dict<std::tuple<SigBit, SigBit, SigBit>, std::tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache; - dict<SigBit, std::tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache; + dict<tuple<SigBit, SigBit, SigBit>, tuple<SigBit, pool<SigBit>, bool>> decode_mux_cache; + dict<SigBit, tuple<SigBit, SigBit, SigBit>> decode_mux_reverse_cache; int decode_mux_counter; bool use_mux4; @@ -142,7 +142,7 @@ struct MuxcoverWorker if (A == B) return 0; - std::tuple<SigBit, SigBit, SigBit> key(A, B, sel); + tuple<SigBit, SigBit, SigBit> key(A, B, sel); if (decode_mux_cache.count(key) == 0) { auto &entry = decode_mux_cache[key]; std::get<0>(entry) = module->addWire(NEW_ID); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 0fb5b3741..956cd48fe 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -247,7 +247,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool is_ne = cell->type == "$ne" || cell->type == "$nex"; - RTLIL::SigSpec xor_out = module->addWire(NEW_ID, std::max(GetSize(sig_a), GetSize(sig_b))); + RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); xor_cell->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src")); simplemap_bitop(module, xor_cell); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index fd5a32e4f..a8fcac9bc 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -256,7 +256,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, case 2: n = xorshift32(GetSize(sig)); m = xorshift32(GetSize(sig)); - for (int i = std::min(n, m); i < std::max(n, m); i++) + for (int i = min(n, m); i < max(n, m); i++) sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0; break; } |