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-rw-r--r--passes/techmap/dfflibmap.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index c8104fb7e..71d708c18 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -478,11 +478,15 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
auto cell_type = cell->type;
auto cell_name = cell->name;
auto cell_connections = cell->connections();
+ std::string src = cell->attributes["\\src"].decode_string();
+
module->remove(cell);
cell_mapping &cm = cell_mappings[cell_type];
RTLIL::Cell *new_cell = module->addCell(cell_name, prepare_mode ? cm.cell_name : "\\" + cm.cell_name);
+ if (!src.empty()) new_cell->attributes["\\src"] = src;
+
bool has_q = false, has_qn = false;
for (auto &port : cm.ports) {
if (port.second == 'Q') has_q = true;