1 files changed, 534 insertions, 101 deletions

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 9ad29a8f6..e1baf4e3d 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -22,6 +22,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/utils.h"
 #include "kernel/celltypes.h"
+#include "kernel/timinginfo.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -33,12 +34,69 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
 	return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
 }
 
+void check(RTLIL::Design *design)
+{
+	dict<IdString,IdString> box_lookup;
+	for (auto m : design->modules()) {
+		if (m->name.begins_with("$paramod"))
+			continue;
+
+		auto flop = m->get_bool_attribute(ID(abc9_flop));
+		auto it = m->attributes.find(ID(abc9_box_id));
+		if (!flop) {
+			if (it == m->attributes.end())
+				continue;
+			auto id = it->second.as_int();
+			auto r = box_lookup.insert(std::make_pair(stringf("$__boxid%d", id), m->name));
+			if (!r.second)
+				log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
+						log_id(m), id, log_id(r.first->second));
+		}
+
+		// Make carry in the last PI, and carry out the last PO
+		//   since ABC requires it this way
+		IdString carry_in, carry_out;
+		for (const auto &port_name : m->ports) {
+			auto w = m->wire(port_name);
+			log_assert(w);
+			if (w->get_bool_attribute("\\abc9_carry")) {
+				if (w->port_input) {
+					if (carry_in != IdString())
+						log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
+					carry_in = port_name;
+				}
+				if (w->port_output) {
+					if (carry_out != IdString())
+						log_error("Module '%s' contains more than one (* abc9_carry *) output port.\n", log_id(m));
+					carry_out = port_name;
+				}
+			}
+		}
+
+		if (carry_in != IdString() && carry_out == IdString())
+			log_error("Module '%s' contains an (* abc9_carry *) input port but no output port.\n", log_id(m));
+		if (carry_in == IdString() && carry_out != IdString())
+			log_error("Module '%s' contains an (* abc9_carry *) output port but no input port.\n", log_id(m));
+
+		if (flop) {
+			int num_outputs = 0;
+			for (auto port_name : m->ports) {
+				auto wire = m->wire(port_name);
+				if (wire->port_output) num_outputs++;
+			}
+			if (num_outputs != 1)
+				log_error("Module '%s' with (* abc9_flop *) has %d outputs (expect 1).\n", log_id(m), num_outputs);
+		}
+	}
+}
+
 void mark_scc(RTLIL::Module *module)
 {
 	// For every unique SCC found, (arbitrarily) find the first
-	//   cell in the component, and convert all wires driven by
-	//   its output ports into a new PO, and drive its previous
-	//   sinks with a new PI
+	//   cell in the component, and replace its output connections
+	//   with a new wire driven by the old connection but with a
+	//   special (* abc9_scc *) attribute set (which is used by
+	//   write_xaiger to break this wire into PI and POs)
 	pool<RTLIL::Const> ids_seen;
 	for (auto cell : module->cells()) {
 		auto it = cell->attributes.find(ID(abc9_scc_id));
@@ -52,15 +110,13 @@ void mark_scc(RTLIL::Module *module)
 		for (auto &c : cell->connections_) {
 			if (c.second.is_fully_const()) continue;
 			if (cell->output(c.first)) {
-				SigBit b = c.second.as_bit();
-				Wire *w = b.wire;
-				w->set_bool_attribute(ID::keep);
-				w->attributes[ID(abc9_scc_id)] = id.as_int();
+				Wire *w = module->addWire(NEW_ID, GetSize(c.second));
+				w->set_bool_attribute(ID(abc9_scc));
+				module->connect(w, c.second);
+				c.second = w;
 			}
 		}
 	}
-
-	module->fixup_ports();
 }
 
 void prep_dff(RTLIL::Module *module)
@@ -85,20 +141,9 @@ void prep_dff(RTLIL::Module *module)
 		clkdomain_t key(abc9_clock);
 
 		auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
-		auto r2 YS_ATTRIBUTE(unused) = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
-		log_assert(r2.second);
-
-		Wire *abc9_init_wire = module->wire(stringf("%s.init", cell->name.c_str()));
-		if (abc9_init_wire == NULL)
-			log_error("'%s.init' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-		log_assert(GetSize(abc9_init_wire) == 1);
-		SigSpec abc9_init = assign_map(abc9_init_wire);
-		if (!abc9_init.is_fully_const())
-			log_error("'%s.init' is not a constant wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
-		if (abc9_init == State::S1)
-			log_error("'%s.init' in module '%s' has value 1'b1 which is not supported by 'abc9 -dff'.\n", cell->name.c_str(), log_id(module));
-		r2 = cell->attributes.insert(std::make_pair(ID(abc9_init), abc9_init.as_const()));
+		auto r2  = cell->attributes.insert(ID(abc9_mergeability));;
 		log_assert(r2.second);
+		r2.first->second = r.first->second;
 	}
 
 	RTLIL::Module *holes_module = design->module(stringf("%s$holes", module->name.c_str()));
@@ -169,13 +214,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 			continue;
 
 		auto inst_module = module->design->module(cell->type);
-		bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");
-		bool abc9_flop = false;
-		if (abc9_box) {
-			abc9_flop = inst_module->get_bool_attribute("\\abc9_flop");
-			if (abc9_flop && !dff)
-				continue;
+		bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
+		if (abc9_flop && !dff)
+			continue;
 
+		if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
 			auto r = box_ports.insert(cell->type);
 			if (r.second) {
 				// Make carry in the last PI, and carry out the last PO
@@ -185,25 +228,15 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 					auto w = inst_module->wire(port_name);
 					log_assert(w);
 					if (w->get_bool_attribute("\\abc9_carry")) {
-						if (w->port_input) {
-							if (carry_in != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(inst_module));
+						log_assert(w->port_input != w->port_output);
+						if (w->port_input)
 							carry_in = port_name;
-						}
-						if (w->port_output) {
-							if (carry_out != IdString())
-								log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(inst_module));
+						else if (w->port_output)
 							carry_out = port_name;
-						}
 					}
 					else
 						r.first->second.push_back(port_name);
 				}
-
-				if (carry_in != IdString() && carry_out == IdString())
-					log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(inst_module));
-				if (carry_in == IdString() && carry_out != IdString())
-					log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(inst_module));
 				if (carry_in != IdString()) {
 					r.first->second.push_back(carry_in);
 					r.first->second.push_back(carry_out);
@@ -232,8 +265,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	for (auto &it : bit_users)
 		if (bit_drivers.count(it.first))
 			for (auto driver_cell : bit_drivers.at(it.first))
-			for (auto user_cell : it.second)
-				toposort.edge(driver_cell, user_cell);
+				for (auto user_cell : it.second)
+					toposort.edge(driver_cell, user_cell);
 
 	if (ys_debug(1))
 		toposort.analyze_loops = true;
@@ -259,6 +292,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	holes_module->set_bool_attribute("\\abc9_holes");
 
 	dict<IdString, Cell*> cell_cache;
+	TimingInfo timing;
 
 	int port_id = 1, box_count = 0;
 	for (auto cell_name : toposort.sorted) {
@@ -266,22 +300,25 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 		log_assert(cell);
 
 		RTLIL::Module* box_module = design->module(cell->type);
-		if (!box_module || !box_module->attributes.count("\\abc9_box_id"))
+		if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
 			continue;
 
 		cell->attributes["\\abc9_box_seq"] = box_count++;
 
-		IdString derived_name = box_module->derive(design, cell->parameters);
-		box_module = design->module(derived_name);
+		IdString derived_type = box_module->derive(design, cell->parameters);
+		box_module = design->module(derived_type);
 
-		auto r = cell_cache.insert(derived_name);
+		auto r = cell_cache.insert(derived_type);
 		auto &holes_cell = r.first->second;
 		if (r.second) {
 			if (box_module->has_processes())
 				Pass::call_on_module(design, box_module, "proc");
 
 			if (box_module->get_bool_attribute("\\whitebox")) {
-				holes_cell = holes_module->addCell(cell->name, derived_name);
+				holes_cell = holes_module->addCell(cell->name, derived_type);
+
+				if (box_module->has_processes())
+					Pass::call_on_module(design, box_module, "proc");
 
 				int box_inputs = 0;
 				for (auto port_name : box_ports.at(cell->type)) {
@@ -303,7 +340,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 						}
 					}
 					else if (w->port_output)
-						conn = holes_module->addWire(stringf("%s.%s", derived_name.c_str(), log_id(port_name)), GetSize(w));
+						conn = holes_module->addWire(stringf("%s.%s", derived_type.c_str(), log_id(port_name)), GetSize(w));
 				}
 
 				// For flops only, create an extra 1-bit input that drives a new wire
@@ -342,59 +379,382 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	}
 }
 
-void reintegrate(RTLIL::Module *module)
+void prep_delays(RTLIL::Design *design, bool dff_mode)
 {
-	auto design = module->design;
-	log_assert(design);
+	TimingInfo timing;
+
+	// Derive all Yosys blackbox modules that are not combinatorial abc9 boxes
+	//   (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
+	pool<Module*> flops;
+	std::vector<Cell*> cells;
+	for (auto module : design->selected_modules()) {
+		if (module->processes.size() > 0) {
+			log("Skipping module %s as it contains processes.\n", log_id(module));
+			continue;
+		}
 
-	map_autoidx = autoidx++;
+		for (auto cell : module->cells()) {
+			if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_), ID($__ABC9_DELAY)))
+				continue;
 
-	RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
-	if (mapped_mod == NULL)
-		log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
+			RTLIL::Module* inst_module = module->design->module(cell->type);
+			if (!inst_module)
+				continue;
+			if (!inst_module->get_blackbox_attribute())
+				continue;
+			if (inst_module->attributes.count(ID(abc9_box)))
+				continue;
+			IdString derived_type = inst_module->derive(design, cell->parameters);
+			inst_module = design->module(derived_type);
+			log_assert(inst_module);
+
+			if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
+				flops.insert(inst_module);
+				continue; // do not add $__ABC9_DELAY boxes to flops
+				//   as delays will be captured in the flop box
+			}
 
-	for (auto w : mapped_mod->wires())
-		module->addWire(remap_name(w->name), GetSize(w));
+			if (!timing.count(derived_type))
+				timing.setup_module(inst_module);
 
-	dict<IdString,std::vector<IdString>> box_ports;
+			cells.emplace_back(cell);
+		}
+	}
 
-	for (auto m : design->modules()) {
-		if (!m->attributes.count(ID(abc9_box_id)))
+	// Insert $__ABC9_DELAY cells on all cells that instantiate blackboxes
+	//   with required times
+	for (auto cell : cells) {
+		auto module = cell->module;
+		RTLIL::Module* inst_module = module->design->module(cell->type);
+		log_assert(inst_module);
+		IdString derived_type = inst_module->derive(design, cell->parameters);
+		inst_module = design->module(derived_type);
+		log_assert(inst_module);
+
+		auto &t = timing.at(derived_type).required;
+		for (auto &conn : cell->connections_) {
+			auto port_wire = inst_module->wire(conn.first);
+			if (!port_wire->port_input)
+				continue;
+
+			SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
+			for (int i = 0; i < GetSize(conn.second); i++) {
+				auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
+				if (d == 0)
+					continue;
+
+#ifndef NDEBUG
+				if (ys_debug(1)) {
+					static std::set<std::tuple<IdString,IdString,int>> seen;
+					if (seen.emplace(derived_type, conn.first, i).second) log("%s.%s[%d] abc9_required = %d\n",
+							log_id(cell->type), log_id(conn.first), i, d);
+				}
+#endif
+				auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
+				box->setPort(ID(I), conn.second[i]);
+				box->setPort(ID(O), O[i]);
+				box->setParam(ID(DELAY), d);
+				conn.second[i] = O[i];
+			}
+		}
+	}
+}
+
+void prep_lut(RTLIL::Design *design, int maxlut)
+{
+	TimingInfo timing;
+
+	std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
+	for (auto module : design->modules()) {
+		auto it = module->attributes.find(ID(abc9_lut));
+		if (it == module->attributes.end())
 			continue;
 
-		auto r = box_ports.insert(m->name);
+		auto &t = timing.setup_module(module);
+
+		TimingInfo::NameBit o;
+		std::vector<int> specify;
+		for (const auto &i : t.comb) {
+			auto &d = i.first.second;
+			if (o == TimingInfo::NameBit())
+				o = d;
+			else if (o != d)
+				log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
+			specify.push_back(i.second);
+		}
+
+		if (maxlut && GetSize(specify) > maxlut)
+			continue;
+		// ABC requires non-decreasing LUT input delays
+		std::sort(specify.begin(), specify.end());
+		table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify));
+	}
+	// ABC requires ascending size
+	std::sort(table.begin(), table.end());
+
+	std::stringstream ss;
+	const auto &first = table.front();
+	// If the first entry does not start from a 1-input LUT,
+	//   (as ABC requires) crop the first entry to do so
+	for (int i = 1; i < std::get<0>(first); i++) {
+		ss << "# $__ABC9_LUT" << i << std::endl;
+		ss << i << " " << std::get<2>(first);
+		for (int j = 0; j < i; j++)
+			ss << " " << std::get<3>(first)[j];
+		ss << std::endl;
+	}
+	for (const auto &i : table) {
+		ss << "# " << log_id(std::get<1>(i)) << std::endl;
+		ss << std::get<0>(i) << " " << std::get<2>(i);
+		for (const auto &j : std::get<3>(i))
+			ss << " " << j;
+		ss << std::endl;
+	}
+	design->scratchpad_set_string("abc9_ops.lut_library", ss.str());
+}
+
+void write_lut(RTLIL::Module *module, const std::string &dst) {
+	std::ofstream ofs(dst);
+	log_assert(ofs.is_open());
+	ofs << module->design->scratchpad_get_string("abc9_ops.lut_library");
+	ofs.close();
+}
+
+void prep_box(RTLIL::Design *design, bool dff_mode)
+{
+	TimingInfo timing;
+
+	std::stringstream ss;
+	int abc9_box_id = 1;
+	for (auto module : design->modules()) {
+		auto it = module->attributes.find(ID(abc9_box_id));
+		if (it == module->attributes.end())
+			continue;
+		abc9_box_id = std::max(abc9_box_id, it->second.as_int());
+	}
+
+	dict<IdString,std::vector<IdString>> box_ports;
+	for (auto module : design->modules()) {
+		auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
+		if (abc9_flop) {
+			auto r = module->attributes.insert(ID(abc9_box_id));
+			if (!r.second)
+				continue;
+			r.first->second = abc9_box_id++;
+
+			if (dff_mode) {
+				int num_inputs = 0, num_outputs = 0;
+				for (auto port_name : module->ports) {
+					auto wire = module->wire(port_name);
+					log_assert(GetSize(wire) == 1);
+					if (wire->port_input) num_inputs++;
+					if (wire->port_output) num_outputs++;
+				}
+				log_assert(num_outputs == 1);
+
+				ss << log_id(module) << " " << r.first->second.as_int();
+				ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+				ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
+
+				ss << "#";
+				bool first = true;
+				for (auto port_name : module->ports) {
+					auto wire = module->wire(port_name);
+					if (!wire->port_input)
+						continue;
+					if (first)
+						first = false;
+					else
+						ss << " ";
+					ss << log_id(wire);
+				}
+				ss << " abc9_ff.Q" << std::endl;
+
+				auto &t = timing.setup_module(module).required;
+				first = true;
+				for (auto port_name : module->ports) {
+					auto wire = module->wire(port_name);
+					if (!wire->port_input)
+						continue;
+					if (first)
+						first = false;
+					else
+						ss << " ";
+					log_assert(GetSize(wire) == 1);
+					auto it = t.find(TimingInfo::NameBit(port_name,0));
+					if (it == t.end())
+						// Assume that no setup time means zero
+						ss << 0;
+					else {
+						ss << it->second;
+
+#ifndef NDEBUG
+						if (ys_debug(1)) {
+							static std::set<std::pair<IdString,IdString>> seen;
+							if (seen.emplace(module->name, port_name).second) log("%s.%s abc9_required = %d\n", log_id(module),
+									log_id(port_name), it->second);
+						}
+#endif
+					}
+
+				}
+				// Last input is 'abc9_ff.Q'
+				ss << " 0" << std::endl << std::endl;
+				continue;
+			}
+		}
+		else {
+			if (!module->attributes.erase(ID(abc9_box)))
+				continue;
+
+			auto r = module->attributes.insert(ID(abc9_box_id));
+			if (!r.second)
+				continue;
+			r.first->second = abc9_box_id++;
+		}
+
+		auto r = box_ports.insert(module->name);
 		if (r.second) {
 			// Make carry in the last PI, and carry out the last PO
 			//   since ABC requires it this way
 			IdString carry_in, carry_out;
-			for (const auto &port_name : m->ports) {
-				auto w = m->wire(port_name);
+			for (const auto &port_name : module->ports) {
+				auto w = module->wire(port_name);
 				log_assert(w);
 				if (w->get_bool_attribute("\\abc9_carry")) {
-					if (w->port_input) {
-						if (carry_in != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(m));
+					log_assert(w->port_input != w->port_output);
+					if (w->port_input)
 						carry_in = port_name;
-					}
-					if (w->port_output) {
-						if (carry_out != IdString())
-							log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(m));
+					else if (w->port_output)
 						carry_out = port_name;
-					}
 				}
 				else
 					r.first->second.push_back(port_name);
 			}
 
-			if (carry_in != IdString() && carry_out == IdString())
-				log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(m));
-			if (carry_in == IdString() && carry_out != IdString())
-				log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(m));
 			if (carry_in != IdString()) {
 				r.first->second.push_back(carry_in);
 				r.first->second.push_back(carry_out);
 			}
 		}
+
+		std::vector<SigBit> inputs;
+		std::vector<SigBit> outputs;
+		for (auto port_name : r.first->second) {
+			auto wire = module->wire(port_name);
+			if (wire->port_input)
+				for (int i = 0; i < GetSize(wire); i++)
+					inputs.emplace_back(wire, i);
+			if (wire->port_output)
+				for (int i = 0; i < GetSize(wire); i++)
+					outputs.emplace_back(wire, i);
+		}
+
+		ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int();
+		ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+		ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
+
+		bool first = true;
+		ss << "#";
+		for (const auto &i : inputs) {
+			if (first)
+				first = false;
+			else
+				ss << " ";
+			if (GetSize(i.wire) == 1)
+				ss << log_id(i.wire);
+			else
+				ss << log_id(i.wire) << "[" << i.offset << "]";
+		}
+		ss << std::endl;
+
+		auto &t = timing.setup_module(module).comb;
+		if (!abc9_flop && t.empty())
+			log_warning("(* abc9_box *) module '%s' has no timing (and thus no connectivity) information.\n", log_id(module));
+
+		for (const auto &o : outputs) {
+			first = true;
+			for (const auto &i : inputs) {
+				if (first)
+					first = false;
+				else
+					ss << " ";
+				auto jt = t.find(TimingInfo::BitBit(i,o));
+				if (jt == t.end())
+					ss << "-";
+				else
+					ss << jt->second;
+			}
+			ss << " # ";
+			if (GetSize(o.wire) == 1)
+				ss << log_id(o.wire);
+			else
+				ss << log_id(o.wire) << "[" << o.offset << "]";
+			ss << std::endl;
+
+		}
+		ss << std::endl;
+	}
+
+	// ABC expects at least one box
+	if (ss.tellp() == 0)
+		ss << "(dummy) 1 0 0 0";
+
+	design->scratchpad_set_string("abc9_ops.box_library", ss.str());
+}
+
+void write_box(RTLIL::Module *module, const std::string &dst) {
+	std::ofstream ofs(dst);
+	log_assert(ofs.is_open());
+	ofs << module->design->scratchpad_get_string("abc9_ops.box_library");
+	ofs.close();
+}
+
+void reintegrate(RTLIL::Module *module)
+{
+	auto design = module->design;
+	log_assert(design);
+
+	map_autoidx = autoidx++;
+
+	RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
+	if (mapped_mod == NULL)
+		log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
+
+	for (auto w : mapped_mod->wires())
+		module->addWire(remap_name(w->name), GetSize(w));
+
+	dict<IdString,std::vector<IdString>> box_ports;
+
+	for (auto m : design->modules()) {
+		if (!m->attributes.count(ID(abc9_box_id)))
+			continue;
+
+		auto r = box_ports.insert(m->name);
+		if (!r.second)
+			continue;
+
+		// Make carry in the last PI, and carry out the last PO
+		//   since ABC requires it this way
+		IdString carry_in, carry_out;
+		for (const auto &port_name : m->ports) {
+			auto w = m->wire(port_name);
+			log_assert(w);
+			if (w->get_bool_attribute("\\abc9_carry")) {
+				log_assert(w->port_input != w->port_output);
+				if (w->port_input)
+					carry_in = port_name;
+				else if (w->port_output)
+					carry_out = port_name;
+			}
+			else
+				r.first->second.push_back(port_name);
+		}
+
+		if (carry_in != IdString()) {
+			r.first->second.push_back(carry_in);
+			r.first->second.push_back(carry_out);
+		}
 	}
 
 	std::vector<Cell*> boxes;
@@ -465,16 +825,6 @@ void reintegrate(RTLIL::Module *module)
 		}
 
 		if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
-			// Convert buffer into direct connection
-			if (mapped_cell->type == ID($lut) &&
-					GetSize(mapped_cell->getPort(ID::A)) == 1 &&
-					mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
-				SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
-				SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
-				module->connect(my_y, my_a);
-				log_abort();
-				continue;
-			}
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
 			cell->parameters = mapped_cell->parameters;
 			cell->attributes = mapped_cell->attributes;
@@ -506,12 +856,25 @@ void reintegrate(RTLIL::Module *module)
 		}
 		else {
 			RTLIL::Cell *existing_cell = module->cell(mapped_cell->name);
-			log_assert(existing_cell);
+			if (!existing_cell)
+				log_error("Cannot find existing box cell with name '%s' in original design.\n", log_id(mapped_cell));
+
+			if (existing_cell->type == ID($__ABC9_DELAY)) {
+				SigBit I = mapped_cell->getPort(ID(i));
+				SigBit O = mapped_cell->getPort(ID(o));
+				if (I.wire)
+					I.wire = module->wires_.at(remap_name(I.wire->name));
+				log_assert(O.wire);
+				O.wire = module->wires_.at(remap_name(O.wire->name));
+				module->connect(O, I);
+				continue;
+			}
 
 			RTLIL::Module* box_module = design->module(existing_cell->type);
-			auto it = box_module->attributes.find(ID(abc9_box_id));
-			log_assert(it != box_module->attributes.end());
-			log_assert(mapped_cell->type == stringf("$__boxid%d", it->second.as_int()));
+			IdString derived_type = box_module->derive(design, existing_cell->parameters);
+			RTLIL::Module* derived_module = design->module(derived_type);
+			log_assert(derived_module);
+			log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
 			mapped_cell->type = existing_cell->type;
 
 			RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
@@ -539,7 +902,7 @@ void reintegrate(RTLIL::Module *module)
 			}
 
 			int input_count = 0, output_count = 0;
-			for (const auto &port_name : box_ports.at(cell->type)) {
+			for (const auto &port_name : box_ports.at(derived_type)) {
 				RTLIL::Wire *w = box_module->wire(port_name);
 				log_assert(w);
 
@@ -603,10 +966,8 @@ void reintegrate(RTLIL::Module *module)
 		RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
 		RTLIL::Wire *wire = module->wire(port);
 		log_assert(wire);
-		if (wire->attributes.erase(ID(abc9_scc_id))) {
-			auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
-			log_assert(r);
-		}
+		wire->attributes.erase(ID(abc9_scc));
+
 		RTLIL::Wire *remap_wire = module->wire(remap_name(port));
 		RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
 		log_assert(GetSize(signal) >= GetSize(remap_wire));
@@ -729,6 +1090,14 @@ struct Abc9OpsPass : public Pass {
 		log("mapping, and is expected to be called in conjunction with other operations from\n");
 		log("the `abc9' script pass. Only fully-selected modules are supported.\n");
 		log("\n");
+		log("    -check\n");
+		log("        check that the design is valid, e.g. (* abc9_box_id *) values are unique,\n");
+		log("        (* abc9_carry *) is only given for one input/output port, etc.\n");
+		log("\n");
+		log("    -prep_delays\n");
+		log("        insert `$__ABC9_DELAY' blackbox cells into the design to account for\n");
+		log("        certain required times.\n");
+		log("\n");
 		log("    -mark_scc\n");
 		log("        for an arbitrarily chosen cell in each unique SCC of each selected module\n");
 		log("        (tagged with an (* abc9_scc_id = <int> *) attribute), temporarily mark all\n");
@@ -742,13 +1111,27 @@ struct Abc9OpsPass : public Pass {
 		log("        whiteboxes.\n");
 		log("\n");
 		log("    -dff\n");
-		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
-		log("        during -prep_xaiger.\n");
+		log("        consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
+		log("        during -prep_{delays,xaiger,box}.\n");
 		log("\n");
 		log("    -prep_dff\n");
 		log("        compute the clock domain and initial value of each flop in the design.\n");
 		log("        process the '$holes' module to support clock-enable functionality.\n");
 		log("\n");
+		log("    -prep_lut <maxlut>\n");
+		log("        pre-compute the lut library by analysing all modules marked with\n");
+		log("        (* abc9_lut=<area> *).\n");
+		log("\n");
+		log("    -write_lut <dst>\n");
+		log("        write the pre-computed lut library to <dst>.\n");
+		log("\n");
+		log("    -prep_box\n");
+		log("        pre-compute the box library by analysing all modules marked with\n");
+		log("        (* abc9_box *).\n");
+		log("\n");
+		log("    -write_box <dst>\n");
+		log("        write the pre-computed box library to <dst>.\n");
+		log("\n");
 		log("    -reintegrate\n");
 		log("        for each selected module, re-intergrate the module '<module-name>$abc9'\n");
 		log("        by first recovering ABC9 boxes, and then stitching in the remaining primary\n");
@@ -759,15 +1142,26 @@ struct Abc9OpsPass : public Pass {
 	{
 		log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
 
+		bool check_mode = false;
+		bool prep_delays_mode = false;
 		bool mark_scc_mode = false;
 		bool prep_dff_mode = false;
 		bool prep_xaiger_mode = false;
+		bool prep_lut_mode = false;
+		bool prep_box_mode = false;
 		bool reintegrate_mode = false;
 		bool dff_mode = false;
+		std::string write_lut_dst;
+		int maxlut = 0;
+		std::string write_box_dst;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
+			if (arg == "-check") {
+				check_mode = true;
+				continue;
+			}
 			if (arg == "-mark_scc") {
 				mark_scc_mode = true;
 				continue;
@@ -780,6 +1174,32 @@ struct Abc9OpsPass : public Pass {
 				prep_xaiger_mode = true;
 				continue;
 			}
+			if (arg == "-prep_delays") {
+				prep_delays_mode = true;
+				continue;
+			}
+			if (arg == "-prep_lut" && argidx+1 < args.size()) {
+				prep_lut_mode = true;
+				maxlut = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (arg == "-maxlut" && argidx+1 < args.size()) {
+				continue;
+			}
+			if (arg == "-write_lut" && argidx+1 < args.size()) {
+				write_lut_dst = args[++argidx];
+				rewrite_filename(write_lut_dst);
+				continue;
+			}
+			if (arg == "-prep_box") {
+				prep_box_mode = true;
+				continue;
+			}
+			if (arg == "-write_box" && argidx+1 < args.size()) {
+				write_box_dst = args[++argidx];
+				rewrite_filename(write_box_dst);
+				continue;
+			}
 			if (arg == "-reintegrate") {
 				reintegrate_mode = true;
 				continue;
@@ -792,11 +1212,20 @@ struct Abc9OpsPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
-			log_cmd_error("At least one of -mark_scc, -prep_{xaiger,dff}, -reintegrate must be specified.\n");
+		if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
+			log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
+
+		if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode)
+			log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n");
 
-		if (dff_mode && !prep_xaiger_mode)
-			log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
+		if (check_mode)
+			check(design);
+		if (prep_delays_mode)
+			prep_delays(design, dff_mode);
+		if (prep_lut_mode)
+			prep_lut(design, maxlut);
+		if (prep_box_mode)
+			prep_box(design, dff_mode);
 
 		for (auto mod : design->selected_modules()) {
 			if (mod->get_bool_attribute("\\abc9_holes"))
@@ -810,6 +1239,10 @@ struct Abc9OpsPass : public Pass {
 			if (!design->selected_whole_module(mod))
 				log_error("Can't handle partially selected module %s!\n", log_id(mod));
 
+			if (!write_lut_dst.empty())
+				write_lut(mod, write_lut_dst);
+			if (!write_box_dst.empty())
+				write_box(mod, write_box_dst);
 			if (mark_scc_mode)
 				mark_scc(mod);
 			if (prep_dff_mode)