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-rw-r--r--passes/sat/freduce.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index da9345855..d5336ca01 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -708,7 +708,7 @@ struct FreduceWorker
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
- for (auto &port : drv->connections())
+ for (auto &port : drv->connections_)
if (ct.cell_output(drv->type, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);