1 files changed, 16 insertions, 16 deletions

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index b012bc6a4..9427547f3 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -116,7 +116,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
 		info.cell = it.second;
 
 		if (info.cell->type == "$dff") {
-			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
 			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
 			std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
@@ -128,8 +128,8 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
 		}
 
 		if (info.cell->type == "$adff") {
-			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->getPort("\\ARST")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
+			info.bit_arst = sigmap(info.cell->getPort("\\ARST")).as_bit();
 			info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
 			info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
 			std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
@@ -144,21 +144,21 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
 		}
 
 		if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
-			info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
 			info.clk_polarity = info.cell->type == "$_DFF_P_";
-			info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
+			info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
+			bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
 			continue;
 		}
 
 		if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
-			info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
-			info.bit_arst = sigmap(info.cell->getPort("\\R")).to_single_sigbit();
+			info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
+			info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit();
 			info.clk_polarity = info.cell->type[6] == 'P';
 			info.arst_polarity = info.cell->type[7] == 'P';
 			info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
-			info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
-			bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
+			info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
+			bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
 			continue;
 		}
 	}
@@ -237,8 +237,8 @@ struct ExposePass : public Pass {
 		log("        signal path at that wire.\n");
 		log("\n");
 		log("    -shared\n");
-		log("        only expose those signals that are shared ammong the selected modules.\n");
-		log("        this is useful for preparing modules for equivialence checking.\n");
+		log("        only expose those signals that are shared among the selected modules.\n");
+		log("        this is useful for preparing modules for equivalence checking.\n");
 		log("\n");
 		log("    -evert\n");
 		log("        also turn connections to instances of other modules to additional\n");
@@ -262,7 +262,7 @@ struct ExposePass : public Pass {
 		bool flag_evert_dff = false;
 		std::string sep = ".";
 
-		log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
+		log_header(design, "Executing EXPOSE pass (exposing internal signals as outputs).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -646,5 +646,5 @@ struct ExposePass : public Pass {
 		}
 	}
 } ExposePass;
- 
+
 PRIVATE_NAMESPACE_END