diff options
Diffstat (limited to 'passes/sat/eval.cc')
| -rw-r--r-- | passes/sat/eval.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 148480d55..f910ea80d 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -153,11 +153,11 @@ struct VlogHammerReporter ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals)); - std::vector<int> y_vec = satgen.importDefSigSpec(module->wire("\\y")); + std::vector<int> y_vec = satgen.importDefSigSpec(module->wire(ID(y))); std::vector<bool> y_values; if (model_undef) { - std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire("\\y")); + std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire(ID(y))); y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end()); } @@ -268,10 +268,10 @@ struct VlogHammerReporter } } - if (module->wire("\\y") == nullptr) + if (module->wire(ID(y)) == nullptr) log_error("No output wire (y) found in module %s!\n", log_id(module->name)); - RTLIL::SigSpec sig(module->wire("\\y")); + RTLIL::SigSpec sig(module->wire(ID(y))); RTLIL::SigSpec undef; while (!ce.eval(sig, undef)) { |