1 files changed, 27 insertions, 12 deletions

diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index dff68159f..0c8fb83dc 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -61,13 +61,28 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
 					log_cmd_error("Failed to get a constant init value for %s: %s\n", log_signal(lhs), log_signal(rhs));
 
 				int offset = 0;
-				for (auto &lhs_c : lhs.chunks()) {
-					if (lhs_c.wire != NULL) {
-						RTLIL::SigSpec value = rhs.extract(offset, lhs_c.width);
-						if (value.size() != lhs_c.wire->width)
-							log_cmd_error("Init value is not for the entire wire: %s = %s\n", log_signal(lhs_c), log_signal(value));
-						log("  Setting init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(value));
-						lhs_c.wire->attributes["\\init"] = value.as_const();
+				for (auto &lhs_c : lhs.chunks())
+				{
+					if (lhs_c.wire != nullptr)
+					{
+						SigSpec valuesig = rhs.extract(offset, lhs_c.width);
+						if (!valuesig.is_fully_const())
+							log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
+
+						Const value = valuesig.as_const();
+						Const &wireinit = lhs_c.wire->attributes["\\init"];
+
+						while (GetSize(wireinit.bits) < lhs_c.wire->width)
+							wireinit.bits.push_back(State::Sx);
+
+						for (int i = 0; i < lhs_c.width; i++) {
+							auto &initbit = wireinit.bits[i + lhs_c.offset];
+							if (initbit != State::Sx && initbit != value[i])
+								log_cmd_error("Conflicting initialization values for %s.\n", log_signal(lhs_c));
+							initbit = value[i];
+						}
+
+						log("  Set init value: %s = %s\n", log_signal(lhs_c.wire), log_signal(wireinit));
 					}
 					offset += lhs_c.width;
 				}
@@ -93,14 +108,14 @@ struct ProcInitPass : public Pass {
 		log("\n");
 		log("    proc_init [selection]\n");
 		log("\n");
-		log("This pass extracts the 'init' actions from processes (generated from verilog\n");
+		log("This pass extracts the 'init' actions from processes (generated from Verilog\n");
 		log("'initial' blocks) and sets the initial value to the 'init' attribute on the\n");
 		log("respective wire.\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PROC_INIT pass (extract init attributes).\n");
+		log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
 
 		extra_args(args, 1, design);
 
@@ -111,5 +126,5 @@ struct ProcInitPass : public Pass {
 						proc_init(mod, proc_it.second);
 	}
 } ProcInitPass;
- 
+
 PRIVATE_NAMESPACE_END