1 files changed, 399 insertions, 90 deletions

diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 74b049bb6..bf406bcd8 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -22,22 +22,27 @@
 #include "kernel/sigtools.h"
 #include "kernel/modtools.h"
 #include "kernel/utils.h"
+#include "kernel/macc.h"
 
+USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+typedef RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell> cell_ptr_cmp;
+typedef std::pair<RTLIL::SigSpec, RTLIL::Const> ssc_pair_t;
+
 struct ShareWorkerConfig
 {
 	int limit;
 	bool opt_force;
 	bool opt_aggressive;
 	bool opt_fast;
-	std::set<RTLIL::IdString> generic_uni_ops, generic_bin_ops, generic_cbin_ops;
+	pool<RTLIL::IdString> generic_uni_ops, generic_bin_ops, generic_cbin_ops, generic_other_ops;
 };
 
 struct ShareWorker
 {
 	ShareWorkerConfig config;
-	std::set<RTLIL::IdString> generic_ops;
+	pool<RTLIL::IdString> generic_ops;
 
 	RTLIL::Design *design;
 	RTLIL::Module *module;
@@ -46,30 +51,32 @@ struct ShareWorker
 	ModWalker modwalker;
 	ModIndex mi;
 
-	std::set<RTLIL::Cell*> cells_to_remove;
-	std::set<RTLIL::Cell*> recursion_state;
+	pool<RTLIL::Cell*> cells_to_remove;
+	pool<RTLIL::Cell*> recursion_state;
 
 	SigMap topo_sigmap;
-	std::map<RTLIL::Cell*, std::set<RTLIL::Cell*>> topo_cell_drivers;
-	std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> topo_bit_drivers;
+	std::map<RTLIL::Cell*, std::set<RTLIL::Cell*, cell_ptr_cmp>, cell_ptr_cmp> topo_cell_drivers;
+	std::map<RTLIL::SigBit, std::set<RTLIL::Cell*, cell_ptr_cmp>> topo_bit_drivers;
+
+	std::vector<std::pair<RTLIL::SigBit, RTLIL::SigBit>> exclusive_ctrls;
 
 
 	// ------------------------------------------------------------------------------
 	// Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree
 	// ------------------------------------------------------------------------------
 
-	std::set<RTLIL::SigBit> terminal_bits;
+	pool<RTLIL::SigBit> terminal_bits;
 
 	void find_terminal_bits()
 	{
-		std::set<RTLIL::SigBit> queue_bits;
-		std::set<RTLIL::Cell*> visited_cells;
+		pool<RTLIL::SigBit> queue_bits;
+		pool<RTLIL::Cell*> visited_cells;
 
 		queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
 
 		for (auto &it : module->cells_)
 			if (!fwd_ct.cell_known(it.second->type)) {
-				std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
+				pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second];
 				queue_bits.insert(bits.begin(), bits.end());
 			}
 
@@ -77,19 +84,19 @@ struct ShareWorker
 
 		while (!queue_bits.empty())
 		{
-			std::set<ModWalker::PortBit> portbits;
+			pool<ModWalker::PortBit> portbits;
 			modwalker.get_drivers(portbits, queue_bits);
 			queue_bits.clear();
 
 			for (auto &pbit : portbits) {
 				if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux") {
-					std::set<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_set();
+					pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort("\\S")).to_sigbit_pool();
 					terminal_bits.insert(bits.begin(), bits.end());
 					queue_bits.insert(bits.begin(), bits.end());
 					visited_cells.insert(pbit.cell);
 				}
 				if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
-					std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
+					pool<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
 					terminal_bits.insert(bits.begin(), bits.end());
 					queue_bits.insert(bits.begin(), bits.end());
 					visited_cells.insert(pbit.cell);
@@ -100,17 +107,251 @@ struct ShareWorker
 
 
 	// ---------------------------------------------------
+	// Code for sharing and comparing MACC cells
+	// ---------------------------------------------------
+
+	static int bits_macc_port(const Macc::port_t &p, int width)
+	{
+		if (GetSize(p.in_a) == 0 || GetSize(p.in_b) == 0)
+			return std::min(std::max(GetSize(p.in_a), GetSize(p.in_b)), width);
+		return std::min(GetSize(p.in_a), width) * std::min(GetSize(p.in_b), width) / 2;
+	}
+
+	static int bits_macc(const Macc &m, int width)
+	{
+		int bits = GetSize(m.bit_ports);
+		for (auto &p : m.ports)
+			bits += bits_macc_port(p, width);
+		return bits;
+	}
+
+	static int bits_macc(RTLIL::Cell *c)
+	{
+		Macc m(c);
+		int width = GetSize(c->getPort("\\Y"));
+		return bits_macc(m, width);
+	}
+
+	static bool cmp_macc_ports(const Macc::port_t &p1, const Macc::port_t &p2)
+	{
+		bool mul1 = GetSize(p1.in_a) && GetSize(p1.in_b);
+		bool mul2 = GetSize(p2.in_a) && GetSize(p2.in_b);
+
+		int w1 = mul1 ? GetSize(p1.in_a) * GetSize(p1.in_b) : GetSize(p1.in_a) + GetSize(p1.in_b);
+		int w2 = mul2 ? GetSize(p2.in_a) * GetSize(p2.in_b) : GetSize(p2.in_a) + GetSize(p2.in_b);
+
+		if (mul1 != mul2)
+			return mul1;
+
+		if (w1 != w2)
+			return w1 > w2;
+
+		if (p1.is_signed != p2.is_signed)
+			return p1.is_signed < p2.is_signed;
+
+		if (p1.do_subtract != p2.do_subtract)
+			return p1.do_subtract < p2.do_subtract;
+
+		if (p1.in_a != p2.in_a)
+			return p1.in_a < p2.in_a;
+
+		if (p1.in_b != p2.in_b)
+			return p1.in_b < p2.in_b;
+
+		return false;
+	}
+
+	int share_macc_ports(Macc::port_t &p1, Macc::port_t &p2, int w1, int w2,
+			RTLIL::SigSpec act = RTLIL::SigSpec(), Macc *supermacc = nullptr, pool<RTLIL::Cell*> *supercell_aux = nullptr)
+	{
+		if (p1.do_subtract != p2.do_subtract)
+			return -1;
+
+		bool mul1 = GetSize(p1.in_a) && GetSize(p1.in_b);
+		bool mul2 = GetSize(p2.in_a) && GetSize(p2.in_b);
+
+		if (mul1 != mul2)
+			return -1;
+
+		bool force_signed = false, force_not_signed = false;
+
+		if ((GetSize(p1.in_a) && GetSize(p1.in_a) < w1) || (GetSize(p1.in_b) && GetSize(p1.in_b) < w1)) {
+			if (p1.is_signed)
+				force_signed = true;
+			else
+				force_not_signed = true;
+		}
+
+		if ((GetSize(p2.in_a) && GetSize(p2.in_a) < w2) || (GetSize(p2.in_b) && GetSize(p2.in_b) < w2)) {
+			if (p2.is_signed)
+				force_signed = true;
+			else
+				force_not_signed = true;
+		}
+
+		if (force_signed && force_not_signed)
+			return -1;
+
+		if (supermacc)
+		{
+			RTLIL::SigSpec sig_a1 = p1.in_a, sig_b1 = p1.in_b;
+			RTLIL::SigSpec sig_a2 = p2.in_a, sig_b2 = p2.in_b;
+
+			RTLIL::SigSpec sig_a = GetSize(sig_a1) > GetSize(sig_a2) ? sig_a1 : sig_a2;
+			RTLIL::SigSpec sig_b = GetSize(sig_b1) > GetSize(sig_b2) ? sig_b1 : sig_b2;
+
+			sig_a1.extend_u0(GetSize(sig_a), p1.is_signed);
+			sig_b1.extend_u0(GetSize(sig_b), p1.is_signed);
+
+			sig_a2.extend_u0(GetSize(sig_a), p2.is_signed);
+			sig_b2.extend_u0(GetSize(sig_b), p2.is_signed);
+
+			if (supercell_aux && GetSize(sig_a)) {
+				sig_a = module->addWire(NEW_ID, GetSize(sig_a));
+				supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a));
+			}
+
+			if (supercell_aux && GetSize(sig_b)) {
+				sig_b = module->addWire(NEW_ID, GetSize(sig_b));
+				supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b));
+			}
+
+			Macc::port_t p;
+			p.in_a = sig_a;
+			p.in_b = sig_b;
+			p.is_signed = force_signed;
+			p.do_subtract = p1.do_subtract;
+			supermacc->ports.push_back(p);
+		}
+
+		int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * std::max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1);
+
+		for (int i = 0; i < std::min(GetSize(p1.in_a), GetSize(p2.in_a)); i++)
+			if (p1.in_a[i] == p2.in_a[i] && score > 0)
+				score--;
+
+		for (int i = 0; i < std::min(GetSize(p1.in_b), GetSize(p2.in_b)); i++)
+			if (p1.in_b[i] == p2.in_b[i] && score > 0)
+				score--;
+
+		return score;
+	}
+
+	int share_macc(RTLIL::Cell *c1, RTLIL::Cell *c2,
+			RTLIL::SigSpec act = RTLIL::SigSpec(), RTLIL::Cell *supercell = nullptr, pool<RTLIL::Cell*> *supercell_aux = nullptr)
+	{
+		Macc m1(c1), m2(c2), supermacc;
+
+		int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y"));
+		int width = std::max(w1, w2);
+
+		m1.optimize(w1);
+		m2.optimize(w2);
+
+		std::sort(m1.ports.begin(), m1.ports.end(), cmp_macc_ports);
+		std::sort(m2.ports.begin(), m2.ports.end(), cmp_macc_ports);
+
+		std::set<int> m1_unmapped, m2_unmapped;
+
+		for (int i = 0; i < GetSize(m1.ports); i++)
+			m1_unmapped.insert(i);
+
+		for (int i = 0; i < GetSize(m2.ports); i++)
+			m2_unmapped.insert(i);
+
+		while (1)
+		{
+			int best_i = -1, best_j = -1, best_score = 0;
+
+			for (int i : m1_unmapped)
+			for (int j : m2_unmapped) {
+				int score = share_macc_ports(m1.ports[i], m2.ports[j], w1, w2);
+				if (score >= 0 && (best_i < 0 || best_score > score))
+					best_i = i, best_j = j, best_score = score;
+			}
+
+			if (best_i >= 0) {
+				m1_unmapped.erase(best_i);
+				m2_unmapped.erase(best_j);
+				share_macc_ports(m1.ports[best_i], m2.ports[best_j], w1, w2, act, &supermacc, supercell_aux);
+			} else
+				break;
+		}
+
+		for (int i : m1_unmapped)
+		{
+			RTLIL::SigSpec sig_a = m1.ports[i].in_a;
+			RTLIL::SigSpec sig_b = m1.ports[i].in_b;
+
+			if (supercell_aux && GetSize(sig_a)) {
+				sig_a = module->addWire(NEW_ID, GetSize(sig_a));
+				supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.ports[i].in_a, act, sig_a));
+			}
+
+			if (supercell_aux && GetSize(sig_b)) {
+				sig_b = module->addWire(NEW_ID, GetSize(sig_b));
+				supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.ports[i].in_b, act, sig_b));
+			}
+
+			Macc::port_t p;
+			p.in_a = sig_a;
+			p.in_b = sig_b;
+			p.is_signed = m1.ports[i].is_signed;
+			p.do_subtract = m1.ports[i].do_subtract;
+			supermacc.ports.push_back(p);
+		}
+
+		for (int i : m2_unmapped)
+		{
+			RTLIL::SigSpec sig_a = m2.ports[i].in_a;
+			RTLIL::SigSpec sig_b = m2.ports[i].in_b;
+
+			if (supercell_aux && GetSize(sig_a)) {
+				sig_a = module->addWire(NEW_ID, GetSize(sig_a));
+				supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
+			}
+
+			if (supercell_aux && GetSize(sig_b)) {
+				sig_b = module->addWire(NEW_ID, GetSize(sig_b));
+				supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
+			}
+
+			Macc::port_t p;
+			p.in_a = sig_a;
+			p.in_b = sig_b;
+			p.is_signed = m2.ports[i].is_signed;
+			p.do_subtract = m2.ports[i].do_subtract;
+			supermacc.ports.push_back(p);
+		}
+
+		if (supercell)
+		{
+			RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width);
+
+			supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort("\\Y")));
+			supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort("\\Y")));
+
+			supercell->setParam("\\Y_WIDTH", width);
+			supercell->setPort("\\Y", sig_y);
+
+			supermacc.optimize(width);
+			supermacc.to_cell(supercell);
+		}
+
+		return bits_macc(supermacc, width);
+	}
+
+
+	// ---------------------------------------------------
 	// Find shareable cells and compatible groups of cells
 	// ---------------------------------------------------
 
-	std::set<RTLIL::Cell*, RTLIL::sort_by_name_str<RTLIL::Cell>> shareable_cells;
+	pool<RTLIL::Cell*> shareable_cells;
 
 	void find_shareable_cells()
 	{
-		for (auto &it : module->cells_)
+		for (auto cell : module->cells())
 		{
-			RTLIL::Cell *cell = it.second;
-
 			if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type))
 				continue;
 
@@ -128,7 +369,9 @@ struct ShareWorker
 			}
 
 			if (cell->type == "$memrd") {
-				if (!cell->parameters.at("\\CLK_ENABLE").as_bool())
+				if (cell->parameters.at("\\CLK_ENABLE").as_bool())
+					continue;
+				if (config.opt_aggressive || !modwalker.sigmap(cell->getPort("\\ADDR")).is_fully_const())
 					shareable_cells.insert(cell);
 				continue;
 			}
@@ -146,7 +389,7 @@ struct ShareWorker
 			}
 
 			if (generic_ops.count(cell->type)) {
-				if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 10)
+				if (config.opt_aggressive)
 					shareable_cells.insert(cell);
 				continue;
 			}
@@ -183,7 +426,7 @@ struct ShareWorker
 			return true;
 		}
 
-		if (config.generic_bin_ops.count(c1->type))
+		if (config.generic_bin_ops.count(c1->type) || c1->type == "$alu")
 		{
 			if (!config.opt_aggressive)
 			{
@@ -229,6 +472,14 @@ struct ShareWorker
 			return true;
 		}
 
+		if (c1->type == "$macc")
+		{
+			if (!config.opt_aggressive)
+				if (share_macc(c1, c2) > 2 * std::min(bits_macc(c1), bits_macc(c2))) return false;
+
+			return true;
+		}
+
 		for (auto &it : c1->parameters)
 			if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second)
 				return false;
@@ -253,7 +504,7 @@ struct ShareWorker
 	// Create replacement cell
 	// -----------------------
 
-	RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act, std::set<RTLIL::Cell*> &supercell_aux)
+	RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act, pool<RTLIL::Cell*> &supercell_aux)
 	{
 		log_assert(c1->type == c2->type);
 
@@ -306,7 +557,7 @@ struct ShareWorker
 			return supercell;
 		}
 
-		if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type))
+		if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type) || c1->type == "$alu")
 		{
 			bool modified_src_cells = false;
 
@@ -409,6 +660,8 @@ struct ShareWorker
 			supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b));
 
 			RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
+			RTLIL::Wire *x = c1->type == "$alu" ? module->addWire(NEW_ID, y_width) : nullptr;
+			RTLIL::Wire *co = c1->type == "$alu" ? module->addWire(NEW_ID, y_width) : nullptr;
 
 			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
 			supercell->parameters["\\A_SIGNED"] = a_signed;
@@ -419,15 +672,39 @@ struct ShareWorker
 			supercell->setPort("\\A", a);
 			supercell->setPort("\\B", b);
 			supercell->setPort("\\Y", y);
+			if (c1->type == "$alu") {
+				RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
+				supercell_aux.insert(module->addMux(NEW_ID, c2->getPort("\\CI"), c1->getPort("\\CI"), act, ci));
+				supercell_aux.insert(module->addMux(NEW_ID, c2->getPort("\\BI"), c1->getPort("\\BI"), act, bi));
+				supercell->setPort("\\CI", ci);
+				supercell->setPort("\\BI", bi);
+				supercell->setPort("\\CO", co);
+				supercell->setPort("\\X", x);
+			}
 			supercell->check();
 
 			supercell_aux.insert(module->addPos(NEW_ID, y, y1));
 			supercell_aux.insert(module->addPos(NEW_ID, y, y2));
+			if (c1->type == "$alu") {
+				supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort("\\CO")));
+				supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort("\\CO")));
+				supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort("\\X")));
+				supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort("\\X")));
+			}
 
 			supercell_aux.insert(supercell);
 			return supercell;
 		}
 
+		if (c1->type == "$macc")
+		{
+			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
+			supercell_aux.insert(supercell);
+			share_macc(c1, c2, act, supercell, &supercell_aux);
+			supercell->check();
+			return supercell;
+		}
+
 		if (c1->type == "$memrd")
 		{
 			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
@@ -444,20 +721,20 @@ struct ShareWorker
 	// Finding forbidden control inputs for a cell
 	// -------------------------------------------
 
-	std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> forbidden_controls_cache;
+	std::map<RTLIL::Cell*, pool<RTLIL::SigBit>, cell_ptr_cmp> forbidden_controls_cache;
 
-	const std::set<RTLIL::SigBit> &find_forbidden_controls(RTLIL::Cell *cell)
+	const pool<RTLIL::SigBit> &find_forbidden_controls(RTLIL::Cell *cell)
 	{
 		if (recursion_state.count(cell)) {
-			static std::set<RTLIL::SigBit> empty_controls_set;
+			static pool<RTLIL::SigBit> empty_controls_set;
 			return empty_controls_set;
 		}
 
 		if (forbidden_controls_cache.count(cell))
 			return forbidden_controls_cache.at(cell);
 
-		std::set<ModWalker::PortBit> pbits;
-		std::set<RTLIL::Cell*> consumer_cells;
+		pool<ModWalker::PortBit> pbits;
+		pool<RTLIL::Cell*> consumer_cells;
 
 		modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
 
@@ -471,11 +748,11 @@ struct ShareWorker
 
 		for (auto c : consumer_cells)
 			if (fwd_ct.cell_known(c->type)) {
-				const std::set<RTLIL::SigBit> &bits = find_forbidden_controls(c);
+				const pool<RTLIL::SigBit> &bits = find_forbidden_controls(c);
 				forbidden_controls_cache[cell].insert(bits.begin(), bits.end());
 			}
 
-		log_assert(recursion_state.count(cell));
+		log_assert(recursion_state.count(cell) != 0);
 		recursion_state.erase(cell);
 
 		return forbidden_controls_cache[cell];
@@ -486,14 +763,14 @@ struct ShareWorker
 	// Finding control inputs and activation pattern for a cell
 	// --------------------------------------------------------
 
-	std::map<RTLIL::Cell*, std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>>> activation_patterns_cache;
+	std::map<RTLIL::Cell*, pool<ssc_pair_t>, cell_ptr_cmp> activation_patterns_cache;
 
-	bool sort_check_activation_pattern(std::pair<RTLIL::SigSpec, RTLIL::Const> &p)
+	bool sort_check_activation_pattern(ssc_pair_t &p)
 	{
 		std::map<RTLIL::SigBit, RTLIL::State> p_bits;
 
 		std::vector<RTLIL::SigBit> p_first_bits = p.first;
-		for (int i = 0; i < SIZE(p_first_bits); i++) {
+		for (int i = 0; i < GetSize(p_first_bits); i++) {
 			RTLIL::SigBit b = p_first_bits[i];
 			RTLIL::State v = p.second.bits[i];
 			if (p_bits.count(b) && p_bits.at(b) != v)
@@ -512,30 +789,30 @@ struct ShareWorker
 		return true;
 	}
 
-	void optimize_activation_patterns(std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> & /* patterns */)
+	void optimize_activation_patterns(pool<ssc_pair_t> & /* patterns */)
 	{
 		// TODO: Remove patterns that are contained in other patterns
 		// TODO: Consolidate pairs of patterns that only differ in the value for one signal bit
 	}
 
-	const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent)
+	const pool<ssc_pair_t> &find_cell_activation_patterns(RTLIL::Cell *cell, const char *indent)
 	{
 		if (recursion_state.count(cell)) {
-			static std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> empty_patterns_set;
+			static pool<ssc_pair_t> empty_patterns_set;
 			return empty_patterns_set;
 		}
 
 		if (activation_patterns_cache.count(cell))
 			return activation_patterns_cache.at(cell);
 
-		const std::set<RTLIL::SigBit> &cell_out_bits = modwalker.cell_outputs[cell];
-		std::set<RTLIL::Cell*> driven_cells, driven_data_muxes;
+		const pool<RTLIL::SigBit> &cell_out_bits = modwalker.cell_outputs[cell];
+		pool<RTLIL::Cell*> driven_cells, driven_data_muxes;
 
 		for (auto &bit : cell_out_bits)
 		{
 			if (terminal_bits.count(bit)) {
 				// Terminal cells are always active: unconditional activation pattern
-				activation_patterns_cache[cell].insert(std::pair<RTLIL::SigSpec, RTLIL::Const>());
+				activation_patterns_cache[cell].insert(ssc_pair_t());
 				return activation_patterns_cache.at(cell);
 			}
 			for (auto &pbit : modwalker.signal_consumers[bit]) {
@@ -551,7 +828,7 @@ struct ShareWorker
 
 		for (auto c : driven_data_muxes)
 		{
-			const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &c_patterns = find_cell_activation_patterns(c, indent);
+			const pool<ssc_pair_t> &c_patterns = find_cell_activation_patterns(c, indent);
 
 			bool used_in_a = false;
 			std::set<int> used_in_b_parts;
@@ -565,13 +842,13 @@ struct ShareWorker
 				if (cell_out_bits.count(bit))
 					used_in_a = true;
 
-			for (int i = 0; i < SIZE(sig_b); i++)
+			for (int i = 0; i < GetSize(sig_b); i++)
 				if (cell_out_bits.count(sig_b[i]))
 					used_in_b_parts.insert(i / width);
 
 			if (used_in_a)
 				for (auto p : c_patterns) {
-					for (int i = 0; i < SIZE(sig_s); i++)
+					for (int i = 0; i < GetSize(sig_s); i++)
 						p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
 					if (sort_check_activation_pattern(p))
 						activation_patterns_cache[cell].insert(p);
@@ -586,11 +863,11 @@ struct ShareWorker
 		}
 
 		for (auto c : driven_cells) {
-			const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &c_patterns = find_cell_activation_patterns(c, indent);
+			const pool<ssc_pair_t> &c_patterns = find_cell_activation_patterns(c, indent);
 			activation_patterns_cache[cell].insert(c_patterns.begin(), c_patterns.end());
 		}
 
-		log_assert(recursion_state.count(cell));
+		log_assert(recursion_state.count(cell) != 0);
 		recursion_state.erase(cell);
 
 		optimize_activation_patterns(activation_patterns_cache[cell]);
@@ -604,7 +881,7 @@ struct ShareWorker
 		return activation_patterns_cache[cell];
 	}
 
-	RTLIL::SigSpec bits_from_activation_patterns(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns)
+	RTLIL::SigSpec bits_from_activation_patterns(const pool<ssc_pair_t> &activation_patterns)
 	{
 		std::set<RTLIL::SigBit> all_bits;
 		for (auto &it : activation_patterns) {
@@ -619,15 +896,15 @@ struct ShareWorker
 		return signal;
 	}
 
-	void filter_activation_patterns(std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &out,
-			const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &in, const std::set<RTLIL::SigBit> &filter_bits)
+	void filter_activation_patterns(pool<ssc_pair_t> &out,
+			const pool<ssc_pair_t> &in, const std::set<RTLIL::SigBit> &filter_bits)
 	{
 		for (auto &p : in)
 		{
 			std::vector<RTLIL::SigBit> p_first = p.first;
-			std::pair<RTLIL::SigSpec, RTLIL::Const> new_p;
+			ssc_pair_t new_p;
 
-			for (int i = 0; i < SIZE(p_first); i++)
+			for (int i = 0; i < GetSize(p_first); i++)
 				if (filter_bits.count(p_first[i]) == 0) {
 					new_p.first.append_bit(p_first[i]);
 					new_p.second.bits.push_back(p.second.bits.at(i));
@@ -637,7 +914,7 @@ struct ShareWorker
 		}
 	}
 
-	RTLIL::SigSpec make_cell_activation_logic(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns, std::set<RTLIL::Cell*> &supercell_aux)
+	RTLIL::SigSpec make_cell_activation_logic(const pool<ssc_pair_t> &activation_patterns, pool<RTLIL::Cell*> &supercell_aux)
 	{
 		RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
 
@@ -665,14 +942,14 @@ struct ShareWorker
 		ct.setup_internals();
 		ct.setup_stdcells();
 
-		TopoSort<RTLIL::Cell*> toposort;
+		TopoSort<RTLIL::Cell*, cell_ptr_cmp> toposort;
 		toposort.analyze_loops = false;
 
 		topo_sigmap.set(module);
 		topo_bit_drivers.clear();
 
-		std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bits;
-		std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cells;
+		dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_bits;
+		dict<RTLIL::SigBit, pool<RTLIL::Cell*>> bit_to_cells;
 
 		for (auto cell : module->cells())
 			if (ct.cell_known(cell->type))
@@ -709,7 +986,7 @@ struct ShareWorker
 		return found_scc;
 	}
 
-	bool find_in_input_cone_worker(RTLIL::Cell *root, RTLIL::Cell *needle, std::set<RTLIL::Cell*> &stop)
+	bool find_in_input_cone_worker(RTLIL::Cell *root, RTLIL::Cell *needle, pool<RTLIL::Cell*> &stop)
 	{
 		if (root == needle)
 			return true;
@@ -727,7 +1004,7 @@ struct ShareWorker
 
 	bool find_in_input_cone(RTLIL::Cell *root, RTLIL::Cell *needle)
 	{
-		std::set<RTLIL::Cell*> stop;
+		pool<RTLIL::Cell*> stop;
 		return find_in_input_cone_worker(root, needle, stop);
 	}
 
@@ -737,12 +1014,12 @@ struct ShareWorker
 		ct.setup_internals();
 		ct.setup_stdcells();
 
-		std::set<RTLIL::Cell*> queue, covered;
+		pool<RTLIL::Cell*> queue, covered;
 		queue.insert(cell);
 
 		while (!queue.empty())
 		{
-			std::set<RTLIL::Cell*> new_queue;
+			pool<RTLIL::Cell*> new_queue;
 
 			for (auto c : queue) {
 				if (!ct.cell_known(c->type))
@@ -775,14 +1052,25 @@ struct ShareWorker
 	// Setup and run
 	// -------------
 
+	void remove_cell(Cell *cell)
+	{
+		shareable_cells.erase(cell);
+		forbidden_controls_cache.erase(cell);
+		activation_patterns_cache.erase(cell);
+		module->remove(cell);
+	}
+
 	ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
 			config(config), design(design), module(module), mi(module)
 	{
+	#ifndef NDEBUG
 		bool before_scc = module_has_scc();
+	#endif
 
 		generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
 		generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
 		generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end());
+		generic_ops.insert(config.generic_other_ops.begin(), config.generic_other_ops.end());
 
 		fwd_ct.setup_internals();
 
@@ -805,16 +1093,23 @@ struct ShareWorker
 			return;
 
 		log("Found %d cells in module %s that may be considered for resource sharing.\n",
-				SIZE(shareable_cells), log_id(module));
+				GetSize(shareable_cells), log_id(module));
+
+		for (auto cell : module->cells())
+			if (cell->type == "$pmux")
+				for (auto bit : cell->getPort("\\S"))
+				for (auto other_bit : cell->getPort("\\S"))
+					if (bit < other_bit)
+						exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit));
 
 		while (!shareable_cells.empty() && config.limit != 0)
 		{
 			RTLIL::Cell *cell = *shareable_cells.begin();
 			shareable_cells.erase(cell);
 
-			log("  Analyzing resource sharing options for %s:\n", log_id(cell));
+			log("  Analyzing resource sharing options for %s (%s):\n", log_id(cell), log_id(cell->type));
 
-			const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &cell_activation_patterns = find_cell_activation_patterns(cell, "    ");
+			const pool<ssc_pair_t> &cell_activation_patterns = find_cell_activation_patterns(cell, "    ");
 			RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
 
 			if (cell_activation_patterns.empty()) {
@@ -823,12 +1118,12 @@ struct ShareWorker
 				continue;
 			}
 
-			if (cell_activation_patterns.count(std::pair<RTLIL::SigSpec, RTLIL::Const>())) {
+			if (cell_activation_patterns.count(ssc_pair_t())) {
 				log("    Cell is always active. Therefore no sharing is possible.\n");
 				continue;
 			}
 
-			log("    Found %d activation_patterns using ctrl signal %s.\n", SIZE(cell_activation_patterns), log_signal(cell_activation_signals));
+			log("    Found %d activation_patterns using ctrl signal %s.\n", GetSize(cell_activation_patterns), log_signal(cell_activation_signals));
 
 			std::vector<RTLIL::Cell*> candidates;
 			find_shareable_partners(candidates, cell);
@@ -838,16 +1133,16 @@ struct ShareWorker
 				continue;
 			}
 
-			log("    Found %d candidates:", SIZE(candidates));
+			log("    Found %d candidates:", GetSize(candidates));
 			for (auto c : candidates)
 				log(" %s", log_id(c));
 			log("\n");
 
 			for (auto other_cell : candidates)
 			{
-				log("    Analyzing resource sharing with %s:\n", log_id(other_cell));
+				log("    Analyzing resource sharing with %s (%s):\n", log_id(other_cell), log_id(other_cell->type));
 
-				const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, "      ");
+				const pool<ssc_pair_t> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell, "      ");
 				RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
 
 				if (other_cell_activation_patterns.empty()) {
@@ -857,17 +1152,17 @@ struct ShareWorker
 					continue;
 				}
 
-				if (other_cell_activation_patterns.count(std::pair<RTLIL::SigSpec, RTLIL::Const>())) {
+				if (other_cell_activation_patterns.count(ssc_pair_t())) {
 					log("      Cell is always active. Therefore no sharing is possible.\n");
 					shareable_cells.erase(other_cell);
 					continue;
 				}
 
 				log("      Found %d activation_patterns using ctrl signal %s.\n",
-						SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals));
+						GetSize(other_cell_activation_patterns), log_signal(other_cell_activation_signals));
 
-				const std::set<RTLIL::SigBit> &cell_forbidden_controls = find_forbidden_controls(cell);
-				const std::set<RTLIL::SigBit> &other_cell_forbidden_controls = find_forbidden_controls(other_cell);
+				const pool<RTLIL::SigBit> &cell_forbidden_controls = find_forbidden_controls(cell);
+				const pool<RTLIL::SigBit> &other_cell_forbidden_controls = find_forbidden_controls(other_cell);
 
 				std::set<RTLIL::SigBit> union_forbidden_controls;
 				union_forbidden_controls.insert(cell_forbidden_controls.begin(), cell_forbidden_controls.end());
@@ -876,8 +1171,8 @@ struct ShareWorker
 				if (!union_forbidden_controls.empty())
 					log("      Forbidden control signals for this pair of cells: %s\n", log_signal(union_forbidden_controls));
 
-				std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> filtered_cell_activation_patterns;
-				std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> filtered_other_cell_activation_patterns;
+				pool<ssc_pair_t> filtered_cell_activation_patterns;
+				pool<ssc_pair_t> filtered_other_cell_activation_patterns;
 
 				filter_activation_patterns(filtered_cell_activation_patterns, cell_activation_patterns, union_forbidden_controls);
 				filter_activation_patterns(filtered_other_cell_activation_patterns, other_cell_activation_patterns, union_forbidden_controls);
@@ -885,10 +1180,10 @@ struct ShareWorker
 				optimize_activation_patterns(filtered_cell_activation_patterns);
 				optimize_activation_patterns(filtered_other_cell_activation_patterns);
 
-				ezDefaultSAT ez;
-				SatGen satgen(&ez, &modwalker.sigmap);
+				ezSatPtr ez;
+				SatGen satgen(ez.get(), &modwalker.sigmap);
 
-				std::set<RTLIL::Cell*> sat_cells;
+				pool<RTLIL::Cell*> sat_cells;
 				std::set<RTLIL::SigBit> bits_queue;
 
 				std::vector<int> cell_active, other_cell_active;
@@ -896,13 +1191,13 @@ struct ShareWorker
 
 				for (auto &p : filtered_cell_activation_patterns) {
 					log("      Activation pattern for cell %s: %s = %s\n", log_id(cell), log_signal(p.first), log_signal(p.second));
-					cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
+					cell_active.push_back(ez->vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
 					all_ctrl_signals.append(p.first);
 				}
 
 				for (auto &p : filtered_other_cell_activation_patterns) {
 					log("      Activation pattern for cell %s: %s = %s\n", log_id(other_cell), log_signal(p.first), log_signal(p.second));
-					other_cell_active.push_back(ez.vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
+					other_cell_active.push_back(ez->vec_eq(satgen.importSigSpec(p.first), satgen.importSigSpec(p.second)));
 					all_ctrl_signals.append(p.first);
 				}
 
@@ -914,7 +1209,7 @@ struct ShareWorker
 
 				while (!bits_queue.empty())
 				{
-					std::set<ModWalker::PortBit> portbits;
+					pool<ModWalker::PortBit> portbits;
 					modwalker.get_drivers(portbits, bits_queue);
 					bits_queue.clear();
 
@@ -932,34 +1227,44 @@ struct ShareWorker
 						break;
 				}
 
-				if (!ez.solve(ez.expression(ez.OpOr, cell_active))) {
+				for (auto it : exclusive_ctrls)
+					if (satgen.importedSigBit(it.first) && satgen.importedSigBit(it.second)) {
+						log("      Adding exclusive control bits: %s vs. %s\n", log_signal(it.first), log_signal(it.second));
+						int sub1 = satgen.importSigBit(it.first);
+						int sub2 = satgen.importSigBit(it.second);
+						ez->assume(ez->NOT(ez->AND(sub1, sub2)));
+					}
+
+				if (!ez->solve(ez->expression(ez->OpOr, cell_active))) {
 					log("      According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(cell));
 					cells_to_remove.insert(cell);
 					break;
 				}
 
-				if (!ez.solve(ez.expression(ez.OpOr, other_cell_active))) {
+				if (!ez->solve(ez->expression(ez->OpOr, other_cell_active))) {
 					log("      According to the SAT solver the cell %s is never active. Sharing is pointless, we simply remove it.\n", log_id(other_cell));
 					cells_to_remove.insert(other_cell);
 					shareable_cells.erase(other_cell);
 					continue;
 				}
 
-				ez.non_incremental();
+				ez->non_incremental();
 
 				all_ctrl_signals.sort_and_unify();
 				std::vector<int> sat_model = satgen.importSigSpec(all_ctrl_signals);
 				std::vector<bool> sat_model_values;
 
-				ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active)));
+				int sub1 = ez->expression(ez->OpOr, cell_active);
+				int sub2 = ez->expression(ez->OpOr, other_cell_active);
+				ez->assume(ez->AND(sub1, sub2));
 
 				log("      Size of SAT problem: %d cells, %d variables, %d clauses\n",
-						SIZE(sat_cells), ez.numCnfVariables(), ez.numCnfClauses());
+						GetSize(sat_cells), ez->numCnfVariables(), ez->numCnfClauses());
 
-				if (ez.solve(sat_model, sat_model_values)) {
+				if (ez->solve(sat_model, sat_model_values)) {
 					log("      According to the SAT solver this pair of cells can not be shared.\n");
-					log("      Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), SIZE(sat_model_values));
-					for (int i = SIZE(sat_model_values)-1; i >= 0; i--)
+					log("      Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), GetSize(sat_model_values));
+					for (int i = GetSize(sat_model_values)-1; i >= 0; i--)
 						log("%c", sat_model_values[i] ? '1' : '0');
 					log("\n");
 					continue;
@@ -989,7 +1294,7 @@ struct ShareWorker
 					other_cell_select_score += p.first.size();
 
 				RTLIL::Cell *supercell;
-				std::set<RTLIL::Cell*> supercell_aux;
+				pool<RTLIL::Cell*> supercell_aux;
 				if (cell_select_score <= other_cell_select_score) {
 					RTLIL::SigSpec act = make_cell_activation_logic(filtered_cell_activation_patterns, supercell_aux);
 					supercell = make_supercell(cell, other_cell, act, supercell_aux);
@@ -1016,11 +1321,11 @@ struct ShareWorker
 					cells_to_remove.erase(other_cell);
 					shareable_cells.insert(other_cell);
 					for (auto cc : supercell_aux)
-						module->remove(cc);
+						remove_cell(cc);
 					continue;
 				}
 
-				std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> supercell_activation_patterns;
+				pool<ssc_pair_t> supercell_activation_patterns;
 				supercell_activation_patterns.insert(filtered_cell_activation_patterns.begin(), filtered_cell_activation_patterns.end());
 				supercell_activation_patterns.insert(filtered_other_cell_activation_patterns.begin(), filtered_other_cell_activation_patterns.end());
 				optimize_activation_patterns(supercell_activation_patterns);
@@ -1045,17 +1350,19 @@ struct ShareWorker
 		}
 
 		if (!cells_to_remove.empty()) {
-			log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module));
+			log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), log_id(module));
 			for (auto c : cells_to_remove) {
 				log("  Removing cell %s (%s).\n", log_id(c), log_id(c->type));
-				module->remove(c);
+				remove_cell(c);
 			}
 		}
 
 		log_assert(recursion_state.empty());
 
+	#ifndef NDEBUG
 		bool after_scc = before_scc || module_has_scc();
 		log_assert(before_scc == after_scc);
+	#endif
 	}
 };
 
@@ -1137,6 +1444,9 @@ struct SharePass : public Pass {
 		config.generic_cbin_ops.insert("$logic_and");
 		config.generic_cbin_ops.insert("$logic_or");
 
+		config.generic_other_ops.insert("$alu");
+		config.generic_other_ops.insert("$macc");
+
 		log_header("Executing SHARE pass (SAT-based resource sharing).\n");
 
 		size_t argidx;
@@ -1168,4 +1478,3 @@ struct SharePass : public Pass {
 } SharePass;
 
 PRIVATE_NAMESPACE_END
-