diff options
Diffstat (limited to 'passes/opt/opt_reduce.cc')
-rw-r--r-- | passes/opt/opt_reduce.cc | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 332e0443e..6a8d8cabd 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -43,7 +43,7 @@ struct OptReduceWorker return; cells.erase(cell); - RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A))); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); pool<RTLIL::SigBit> new_sig_a_bits; for (auto &bit : sig_a.to_sigbit_set()) @@ -73,8 +73,8 @@ struct OptReduceWorker for (auto child_cell : drivers.find(bit)) { if (child_cell->type == cell->type) { opt_reduce(cells, drivers, child_cell); - if (child_cell->getPort(ID(Y))[0] == bit) { - pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(ID(A))).to_sigbit_pool(); + if (child_cell->getPort(ID::Y)[0] == bit) { + pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(ID::A)).to_sigbit_pool(); new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end()); } else new_sig_a_bits.insert(RTLIL::State::S0); @@ -87,21 +87,21 @@ struct OptReduceWorker RTLIL::SigSpec new_sig_a(new_sig_a_bits); - if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID(A)).size()) { + if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) { log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); did_something = true; total_count++; } - cell->setPort(ID(A), new_sig_a); + cell->setPort(ID::A, new_sig_a); cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size()); return; } void opt_mux(RTLIL::Cell *cell) { - RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID(A))); - RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID(B))); + RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); + RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S))); RTLIL::SigSpec new_sig_b, new_sig_s; @@ -124,14 +124,14 @@ struct OptReduceWorker if (this_s.size() > 1) { RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or)); - reduce_or_cell->setPort(ID(A), this_s); + reduce_or_cell->setPort(ID::A, this_s); reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0); reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1); RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); this_s = RTLIL::SigSpec(reduce_or_wire); - reduce_or_cell->setPort(ID(Y), this_s); + reduce_or_cell->setPort(ID::Y, this_s); } new_sig_b.append(this_b); @@ -147,13 +147,13 @@ struct OptReduceWorker if (new_sig_s.size() == 0) { - module->connect(RTLIL::SigSig(cell->getPort(ID(Y)), cell->getPort(ID(A)))); - assign_map.add(cell->getPort(ID(Y)), cell->getPort(ID(A))); + module->connect(RTLIL::SigSig(cell->getPort(ID::Y), cell->getPort(ID::A))); + assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A)); module->remove(cell); } else { - cell->setPort(ID(B), new_sig_b); + cell->setPort(ID::B, new_sig_b); cell->setPort(ID(S), new_sig_s); if (new_sig_s.size() > 1) { cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size()); @@ -166,9 +166,9 @@ struct OptReduceWorker void opt_mux_bits(RTLIL::Cell *cell) { - std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort(ID(A))).to_sigbit_vector(); - std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort(ID(B))).to_sigbit_vector(); - std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort(ID(Y))).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort(ID::A)).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort(ID::B)).to_sigbit_vector(); + std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort(ID::Y)).to_sigbit_vector(); std::vector<RTLIL::SigBit> new_sig_y; RTLIL::SigSig old_sig_conn; @@ -209,29 +209,29 @@ struct OptReduceWorker if (new_sig_y.size() != sig_y.size()) { log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str()); - log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID(A))), - log_signal(cell->getPort(ID(B))), log_signal(cell->getPort(ID(Y)))); + log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); - cell->setPort(ID(A), RTLIL::SigSpec()); + cell->setPort(ID::A, RTLIL::SigSpec()); for (auto &in_tuple : consolidated_in_tuples) { - RTLIL::SigSpec new_a = cell->getPort(ID(A)); + RTLIL::SigSpec new_a = cell->getPort(ID::A); new_a.append(in_tuple.at(0)); - cell->setPort(ID(A), new_a); + cell->setPort(ID::A, new_a); } - cell->setPort(ID(B), RTLIL::SigSpec()); + cell->setPort(ID::B, RTLIL::SigSpec()); for (int i = 1; i <= cell->getPort(ID(S)).size(); i++) for (auto &in_tuple : consolidated_in_tuples) { - RTLIL::SigSpec new_b = cell->getPort(ID(B)); + RTLIL::SigSpec new_b = cell->getPort(ID::B); new_b.append(in_tuple.at(i)); - cell->setPort(ID(B), new_b); + cell->setPort(ID::B, new_b); } cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size()); - cell->setPort(ID(Y), new_sig_y); + cell->setPort(ID::Y, new_sig_y); - log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID(A))), - log_signal(cell->getPort(ID(B))), log_signal(cell->getPort(ID(Y)))); + log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), + log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y))); log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second)); module->connect(old_sig_conn); @@ -269,12 +269,12 @@ struct OptReduceWorker keep_expanding_mem_wren_sigs = false; for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; - if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Y))))) { - if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID(A)))) || - !mem_wren_sigs.check_all(assign_map(cell->getPort(ID(B))))) + if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) { + if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::A))) || + !mem_wren_sigs.check_all(assign_map(cell->getPort(ID::B)))) keep_expanding_mem_wren_sigs = true; - mem_wren_sigs.add(assign_map(cell->getPort(ID(A)))); - mem_wren_sigs.add(assign_map(cell->getPort(ID(B)))); + mem_wren_sigs.add(assign_map(cell->getPort(ID::A))); + mem_wren_sigs.add(assign_map(cell->getPort(ID::B))); } } } @@ -296,7 +296,7 @@ struct OptReduceWorker RTLIL::Cell *cell = cell_it.second; if (cell->type != type || !design->selected(module, cell)) continue; - drivers.insert(assign_map(cell->getPort(ID(Y))), cell); + drivers.insert(assign_map(cell->getPort(ID::Y)), cell); cells.insert(cell); } @@ -318,7 +318,7 @@ struct OptReduceWorker { // this optimization is to aggressive for most coarse-grain applications. // but we always want it for multiplexers driving write enable ports. - if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Y))))) + if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) opt_mux_bits(cell); opt_mux(cell); |