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-rw-r--r--passes/memory/memory_map.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index a0b808e56..65bccb5ef 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -301,7 +301,7 @@ struct MemoryMapWorker
RTLIL::Wire *w = w_seladdr;
- if (wr_bit != RTLIL::SigSpec(1, 1))
+ if (wr_bit != State::S1)
{
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
c->parameters["\\A_SIGNED"] = RTLIL::Const(0);