1 files changed, 215 insertions, 132 deletions

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index d3cc681a2..40691d160 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -17,170 +17,251 @@
  *
  */
 
-#include "kernel/register.h"
-#include "kernel/log.h"
-#include <stdlib.h>
-#include <sstream>
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
+struct MemoryDffWorker
 {
-	for (auto &conn : module->connections())
-		sig.replace(conn.first, conn.second);
-}
+	Module *module;
+	SigMap sigmap;
 
-bool find_sig_before_dff(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
-{
-	normalize_sig(module, sig);
+	vector<Cell*> dff_cells;
+	dict<SigBit, SigBit> invbits;
+	dict<SigBit, int> sigbit_users_count;
+	dict<SigSpec, Cell*> mux_cells_a, mux_cells_b;
+	pool<Cell*> forward_merged_dffs, candidate_dffs;
+
+	MemoryDffWorker(Module *module) : module(module), sigmap(module) { }
 
-	for (auto &bit : sig)
+	bool find_sig_before_dff(RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
 	{
-		if (bit.wire == NULL)
-			continue;
+		sigmap.apply(sig);
 
-		for (auto cell : dff_cells)
+		for (auto &bit : sig)
 		{
-			if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-				if (cell->getPort("\\CLK") != clk)
-					continue;
-				if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
-					continue;
-			}
-
-			RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
-			normalize_sig(module, q_norm);
-
-			RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
-			if (d.size() != 1)
+			if (bit.wire == NULL)
 				continue;
 
-			bit = d;
-			clk = cell->getPort("\\CLK");
-			clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
-			goto replaced_this_bit;
-		}
+			for (auto cell : dff_cells)
+			{
+				if (after && forward_merged_dffs.count(cell))
+					continue;
 
-		return false;
-	replaced_this_bit:;
-	}
+				SigSpec this_clk = cell->getPort("\\CLK");
+				bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 
-	return true;
-}
+				if (invbits.count(this_clk)) {
+					this_clk = invbits.at(this_clk);
+					this_clk_polarity = !this_clk_polarity;
+				}
 
-void handle_wr_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
-{
-	log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
+				if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
+					if (this_clk != clk)
+						continue;
+					if (this_clk_polarity != clk_polarity)
+						continue;
+				}
 
-	RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
-	bool clk_polarity = 0;
+				RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
+				sigmap.apply(q_norm);
 
-	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
-	if (!find_sig_before_dff(module, dff_cells, sig_addr, clk, clk_polarity)) {
-		log("no (compatible) $dff for address input found.\n");
-		return;
-	}
+				RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
+				if (d.size() != 1)
+					continue;
 
-	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
-	if (!find_sig_before_dff(module, dff_cells, sig_data, clk, clk_polarity)) {
-		log("no (compatible) $dff for data input found.\n");
-		return;
-	}
+				bit = d;
+				clk = this_clk;
+				clk_polarity = this_clk_polarity;
+				candidate_dffs.insert(cell);
+				goto replaced_this_bit;
+			}
 
-	RTLIL::SigSpec sig_en = cell->getPort("\\EN");
-	if (!find_sig_before_dff(module, dff_cells, sig_en, clk, clk_polarity)) {
-		log("no (compatible) $dff for enable input found.\n");
-		return;
-	}
+			return false;
+		replaced_this_bit:;
+		}
 
-	if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
-		cell->setPort("\\CLK", clk);
-		cell->setPort("\\ADDR", sig_addr);
-		cell->setPort("\\DATA", sig_data);
-		cell->setPort("\\EN", sig_en);
-		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
-		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
-		log("merged $dff to cell.\n");
-		return;
+		return true;
 	}
 
-	log("no (compatible) $dff found.\n");
-}
+	void handle_wr_cell(RTLIL::Cell *cell)
+	{
+		log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
 
-void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
-{
-	normalize_sig(module, sig);
-	sig.sort_and_unify();
+		RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
+		bool clk_polarity = 0;
+		candidate_dffs.clear();
 
-	std::stringstream sstr;
-	sstr << "$memory_dff_disconnected$" << (autoidx++);
+		RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+		if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
+			log("no (compatible) $dff for address input found.\n");
+			return;
+		}
 
-	RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
+		RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+		if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
+			log("no (compatible) $dff for data input found.\n");
+			return;
+		}
 
-	for (auto cell : module->cells())
-		if (cell->type == "$dff") {
-			RTLIL::SigSpec new_q = cell->getPort("\\Q");
-			new_q.replace(sig, new_sig);
-			cell->setPort("\\Q", new_q);
+		RTLIL::SigSpec sig_en = cell->getPort("\\EN");
+		if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
+			log("no (compatible) $dff for enable input found.\n");
+			return;
 		}
-}
 
-void handle_rd_cell(RTLIL::Module *module, std::vector<RTLIL::Cell*> &dff_cells, RTLIL::Cell *cell)
-{
-	log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
+		if (clk != RTLIL::SigSpec(RTLIL::State::Sx))
+		{
+			for (auto cell : candidate_dffs)
+				forward_merged_dffs.insert(cell);
+
+			cell->setPort("\\CLK", clk);
+			cell->setPort("\\ADDR", sig_addr);
+			cell->setPort("\\DATA", sig_data);
+			cell->setPort("\\EN", sig_en);
+			cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+
+			log("merged $dff to cell.\n");
+			return;
+		}
 
-	bool clk_polarity = 0;
+		log("no (compatible) $dff found.\n");
+	}
 
-	RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
-	if (find_sig_before_dff(module, dff_cells, sig_data, clk_data, clk_polarity, true) &&
-			clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
+	void disconnect_dff(RTLIL::SigSpec sig)
 	{
-		disconnect_dff(module, sig_data);
-		cell->setPort("\\CLK", clk_data);
-		cell->setPort("\\DATA", sig_data);
-		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
-		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
-		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
-		log("merged data $dff to cell.\n");
-		return;
+		sigmap.apply(sig);
+		sig.sort_and_unify();
+
+		std::stringstream sstr;
+		sstr << "$memory_dff_disconnected$" << (autoidx++);
+
+		RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
+
+		for (auto cell : module->cells())
+			if (cell->type == "$dff") {
+				RTLIL::SigSpec new_q = cell->getPort("\\Q");
+				new_q.replace(sig, new_sig);
+				cell->setPort("\\Q", new_q);
+			}
 	}
 
-	RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
-	RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
-	if (find_sig_before_dff(module, dff_cells, sig_addr, clk_addr, clk_polarity) &&
-			clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
+	void handle_rd_cell(RTLIL::Cell *cell)
 	{
-		cell->setPort("\\CLK", clk_addr);
-		cell->setPort("\\ADDR", sig_addr);
-		cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
-		cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
-		cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
-		log("merged address $dff to cell.\n");
-		return;
-	}
+		log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
 
-	log("no (compatible) $dff found.\n");
-}
+		bool clk_polarity = 0;
 
-void handle_module(RTLIL::Module *module, bool flag_wr_only)
-{
-	std::vector<RTLIL::Cell*> dff_cells;
+		RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
+		RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+
+		for (auto bit : sigmap(sig_data))
+			if (sigbit_users_count[bit] > 1)
+				goto skip_ff_after_read_merging;
 
-	for (auto cell : module->cells())
-		if (cell->type == "$dff")
-			dff_cells.push_back(cell);
+		if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
+		{
+			bool enable_invert = mux_cells_a.count(sig_data) != 0;
+			Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
+			SigSpec check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
+
+			sig_data = sigmap(mux->getPort("\\Y"));
+			for (auto bit : sig_data)
+				if (sigbit_users_count[bit] > 1)
+					goto skip_ff_after_read_merging;
+
+			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
+			{
+				disconnect_dff(sig_data);
+				cell->setPort("\\CLK", clk_data);
+				cell->setPort("\\EN", enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
+				cell->setPort("\\DATA", sig_data);
+				cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+				cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+				cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+				log("merged data $dff with rd enable to cell.\n");
+				return;
+			}
+		}
+		else
+		{
+			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
+			{
+				disconnect_dff(sig_data);
+				cell->setPort("\\CLK", clk_data);
+				cell->setPort("\\EN", State::S1);
+				cell->setPort("\\DATA", sig_data);
+				cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+				cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+				cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+				log("merged data $dff to cell.\n");
+				return;
+			}
+		}
 
-	for (auto cell : module->selected_cells())
-		if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
-			handle_wr_cell(module, dff_cells, cell);
+	skip_ff_after_read_merging:;
+		RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
+		RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+		if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
+				clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
+		{
+			cell->setPort("\\CLK", clk_addr);
+			cell->setPort("\\EN", State::S1);
+			cell->setPort("\\ADDR", sig_addr);
+			cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+			cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
+			log("merged address $dff to cell.\n");
+			return;
+		}
+
+		log("no (compatible) $dff found.\n");
+	}
+
+	void run(bool flag_wr_only)
+	{
+		for (auto wire : module->wires()) {
+			if (wire->port_output)
+				for (auto bit : sigmap(wire))
+					sigbit_users_count[bit]++;
+		}
+
+		for (auto cell : module->cells()) {
+			if (cell->type == "$dff")
+				dff_cells.push_back(cell);
+			if (cell->type == "$mux") {
+				mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
+				mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
+			}
+			if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
+				SigSpec sig_a = cell->getPort("\\A");
+				SigSpec sig_y = cell->getPort("\\Y");
+				if (cell->type == "$not")
+					sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
+				if (cell->type == "$logic_not")
+					sig_y.extend_u0(1);
+				for (int i = 0; i < GetSize(sig_y); i++)
+					invbits[sig_y[i]] = sig_a[i];
+			}
+			for (auto &conn : cell->connections())
+				if (!cell->known() || cell->input(conn.first))
+					for (auto bit : sigmap(conn.second))
+						sigbit_users_count[bit]++;
+		}
 
-	if (!flag_wr_only)
 		for (auto cell : module->selected_cells())
-			if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
-				handle_rd_cell(module, dff_cells, cell);
-}
+			if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+				handle_wr_cell(cell);
+
+		if (!flag_wr_only)
+			for (auto cell : module->selected_cells())
+				if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+					handle_rd_cell(cell);
+	}
+};
 
 struct MemoryDffPass : public Pass {
 	MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
@@ -194,7 +275,7 @@ struct MemoryDffPass : public Pass {
 		log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
 		log("interface and yields a synchronous memory port.\n");
 		log("\n");
-		log("    -wr_only\n");
+		log("    -nordfff\n");
 		log("        do not merge registers on read ports\n");
 		log("\n");
 	}
@@ -202,11 +283,11 @@ struct MemoryDffPass : public Pass {
 	{
 		bool flag_wr_only = false;
 
-		log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
+		log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
-			if (args[argidx] == "-wr_only") {
+			if (args[argidx] == "-nordff" || args[argidx] == "-wr_only") {
 				flag_wr_only = true;
 				continue;
 			}
@@ -214,9 +295,11 @@ struct MemoryDffPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		for (auto mod : design->selected_modules())
-			handle_module(mod, flag_wr_only);
+		for (auto mod : design->selected_modules()) {
+			MemoryDffWorker worker(mod);
+			worker.run(flag_wr_only);
+		}
 	}
 } MemoryDffPass;
- 
+
 PRIVATE_NAMESPACE_END