1 files changed, 53 insertions, 53 deletions

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index be4b3c100..726a5c1ff 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -39,10 +39,10 @@ struct MemoryDffWorker
 	MemoryDffWorker(Module *module) : module(module), sigmap(module)
 	{
 		for (auto wire : module->wires()) {
-			if (wire->attributes.count("\\init") == 0)
+			if (wire->attributes.count(ID::init) == 0)
 				continue;
 			SigSpec sig = sigmap(wire);
-			Const initval = wire->attributes.at("\\init");
+			Const initval = wire->attributes.at(ID::init);
 			for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
 				if (initval[i] == State::S0 || initval[i] == State::S1)
 					init_bits.insert(sig[i]);
@@ -66,8 +66,8 @@ struct MemoryDffWorker
 				if (after && forward_merged_dffs.count(cell))
 					continue;
 
-				SigSpec this_clk = cell->getPort("\\CLK");
-				bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
+				SigSpec this_clk = cell->getPort(ID::CLK);
+				bool this_clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
 
 				if (invbits.count(this_clk)) {
 					this_clk = invbits.at(this_clk);
@@ -81,10 +81,10 @@ struct MemoryDffWorker
 						continue;
 				}
 
-				RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q");
+				RTLIL::SigSpec q_norm = cell->getPort(after ? ID::D : ID::Q);
 				sigmap.apply(q_norm);
 
-				RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D"));
+				RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? ID::Q : ID::D));
 				if (d.size() != 1)
 					continue;
 
@@ -113,19 +113,19 @@ struct MemoryDffWorker
 		bool clk_polarity = 0;
 		candidate_dffs.clear();
 
-		RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+		RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
 		if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
 			log("no (compatible) $dff for address input found.\n");
 			return;
 		}
 
-		RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+		RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
 		if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
 			log("no (compatible) $dff for data input found.\n");
 			return;
 		}
 
-		RTLIL::SigSpec sig_en = cell->getPort("\\EN");
+		RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
 		if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
 			log("no (compatible) $dff for enable input found.\n");
 			return;
@@ -136,12 +136,12 @@ struct MemoryDffWorker
 			for (auto cell : candidate_dffs)
 				forward_merged_dffs.insert(cell);
 
-			cell->setPort("\\CLK", clk);
-			cell->setPort("\\ADDR", sig_addr);
-			cell->setPort("\\DATA", sig_data);
-			cell->setPort("\\EN", sig_en);
-			cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
-			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+			cell->setPort(ID::CLK, clk);
+			cell->setPort(ID::ADDR, sig_addr);
+			cell->setPort(ID::DATA, sig_data);
+			cell->setPort(ID::EN, sig_en);
+			cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+			cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
 
 			log("merged $dff to cell.\n");
 			return;
@@ -161,10 +161,10 @@ struct MemoryDffWorker
 		RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
 
 		for (auto cell : module->cells())
-			if (cell->type == "$dff") {
-				RTLIL::SigSpec new_q = cell->getPort("\\Q");
+			if (cell->type == ID($dff)) {
+				RTLIL::SigSpec new_q = cell->getPort(ID::Q);
 				new_q.replace(sig, new_sig);
-				cell->setPort("\\Q", new_q);
+				cell->setPort(ID::Q, new_q);
 			}
 	}
 
@@ -175,7 +175,7 @@ struct MemoryDffWorker
 		bool clk_polarity = 0;
 
 		RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
-		RTLIL::SigSpec sig_data = cell->getPort("\\DATA");
+		RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
 
 		for (auto bit : sigmap(sig_data))
 			if (sigbit_users_count[bit] > 1)
@@ -189,9 +189,9 @@ struct MemoryDffWorker
 			do {
 				bool enable_invert = mux_cells_a.count(sig_data) != 0;
 				Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
-				check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
-				sig_data = sigmap(mux->getPort("\\Y"));
-				en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
+				check_q.push_back(sigmap(mux->getPort(enable_invert ? ID::B : ID::A)));
+				sig_data = sigmap(mux->getPort(ID::Y));
+				en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort(ID::S)) : mux->getPort(ID::S));
 			} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
 
 			for (auto bit : sig_data)
@@ -202,12 +202,12 @@ struct MemoryDffWorker
 					std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
 			{
 				disconnect_dff(sig_data);
-				cell->setPort("\\CLK", clk_data);
-				cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
-				cell->setPort("\\DATA", sig_data);
-				cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
-				cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
-				cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+				cell->setPort(ID::CLK, clk_data);
+				cell->setPort(ID::EN, en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
+				cell->setPort(ID::DATA, sig_data);
+				cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+				cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+				cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
 				log("merged data $dff with rd enable to cell.\n");
 				return;
 			}
@@ -217,12 +217,12 @@ struct MemoryDffWorker
 			if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
 			{
 				disconnect_dff(sig_data);
-				cell->setPort("\\CLK", clk_data);
-				cell->setPort("\\EN", State::S1);
-				cell->setPort("\\DATA", sig_data);
-				cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
-				cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
-				cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
+				cell->setPort(ID::CLK, clk_data);
+				cell->setPort(ID::EN, State::S1);
+				cell->setPort(ID::DATA, sig_data);
+				cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+				cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+				cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
 				log("merged data $dff to cell.\n");
 				return;
 			}
@@ -230,16 +230,16 @@ struct MemoryDffWorker
 
 	skip_ff_after_read_merging:;
 		RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
-		RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR");
+		RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
 		if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
 				clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
 		{
-			cell->setPort("\\CLK", clk_addr);
-			cell->setPort("\\EN", State::S1);
-			cell->setPort("\\ADDR", sig_addr);
-			cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
-			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
-			cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1);
+			cell->setPort(ID::CLK, clk_addr);
+			cell->setPort(ID::EN, State::S1);
+			cell->setPort(ID::ADDR, sig_addr);
+			cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
+			cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
+			cell->parameters[ID::TRANSPARENT] = RTLIL::Const(1);
 			log("merged address $dff to cell.\n");
 			return;
 		}
@@ -256,18 +256,18 @@ struct MemoryDffWorker
 		}
 
 		for (auto cell : module->cells()) {
-			if (cell->type == "$dff")
+			if (cell->type == ID($dff))
 				dff_cells.push_back(cell);
-			if (cell->type == "$mux") {
-				mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
-				mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
+			if (cell->type == ID($mux)) {
+				mux_cells_a[sigmap(cell->getPort(ID::A))] = cell;
+				mux_cells_b[sigmap(cell->getPort(ID::B))] = cell;
 			}
-			if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
-				SigSpec sig_a = cell->getPort("\\A");
-				SigSpec sig_y = cell->getPort("\\Y");
-				if (cell->type == "$not")
-					sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
-				if (cell->type == "$logic_not")
+			if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) {
+				SigSpec sig_a = cell->getPort(ID::A);
+				SigSpec sig_y = cell->getPort(ID::Y);
+				if (cell->type == ID($not))
+					sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
+				if (cell->type == ID($logic_not))
 					sig_y.extend_u0(1);
 				for (int i = 0; i < GetSize(sig_y); i++)
 					invbits[sig_y[i]] = sig_a[i];
@@ -279,12 +279,12 @@ struct MemoryDffWorker
 		}
 
 		for (auto cell : module->selected_cells())
-			if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+			if (cell->type == ID($memwr) && !cell->parameters[ID::CLK_ENABLE].as_bool())
 				handle_wr_cell(cell);
 
 		if (!flag_wr_only)
 			for (auto cell : module->selected_cells())
-				if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool())
+				if (cell->type == ID($memrd) && !cell->parameters[ID::CLK_ENABLE].as_bool())
 					handle_rd_cell(cell);
 	}
 };