diff options
Diffstat (limited to 'passes/fsm/fsm_expand.cc')
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index a261eb22b..3ded3f377 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -2,11 +2,11 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> - * + * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. - * + * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR @@ -253,12 +253,12 @@ struct FsmExpandPass : public Pass { log("\n"); log("The fsm_extract pass is conservative about the cells that belong to a finite\n"); log("state machine. This pass can be used to merge additional auxiliary gates into\n"); - log("the finate state machine.\n"); + log("the finite state machine.\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n"); + log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n"); extra_args(args, 1, design); for (auto &mod_it : design->modules_) { @@ -275,5 +275,5 @@ struct FsmExpandPass : public Pass { } } } FsmExpandPass; - + PRIVATE_NAMESPACE_END |