1 files changed, 12 insertions, 81 deletions

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 56bc50ced..e15e510be 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -41,16 +41,6 @@ struct EquivMakeWorker
 	pool<SigBit> undriven_bits;
 	SigMap assign_map;
 
-	dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells
-
-	CellTypes comb_ct;
-
-	EquivMakeWorker()
-	{
-		comb_ct.setup_internals();
-		comb_ct.setup_stdcells();
-	}
-
 	void read_blacklists()
 	{
 		for (auto fn : blacklists)
@@ -154,6 +144,7 @@ struct EquivMakeWorker
 	{
 		SigMap assign_map(equiv_mod);
 		SigMap rd_signal_map;
+		SigPool primary_inputs;
 
 		// list of cells without added $equiv cells
 		auto cells_list = equiv_mod->cells().to_vector();
@@ -278,6 +269,9 @@ struct EquivMakeWorker
 				gate_wire->port_input = false;
 				equiv_mod->connect(gold_wire, wire);
 				equiv_mod->connect(gate_wire, wire);
+				primary_inputs.add(assign_map(gold_wire));
+				primary_inputs.add(assign_map(gate_wire));
+				primary_inputs.add(wire);
 			}
 			else
 			{
@@ -309,31 +303,19 @@ struct EquivMakeWorker
 			}
 		}
 
-		init_bit2driven();
-
-		pool<Cell*> visited_cells;
 		for (auto c : cells_list)
 		for (auto &conn : c->connections())
 			if (!ct.cell_output(c->type, conn.first)) {
 				SigSpec old_sig = assign_map(conn.second);
 				SigSpec new_sig = rd_signal_map(old_sig);
-
-				if(old_sig != new_sig) {
-					SigSpec tmp_sig = old_sig;
-					for (int i = 0; i < GetSize(old_sig); i++) {
-						SigBit old_bit = old_sig[i], new_bit = new_sig[i];
-
-						visited_cells.clear();
-						if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
-							continue;
-
-						log("Changing input %s of cell %s (%s): %s -> %s\n",
-								log_id(conn.first), log_id(c), log_id(c->type),
-								log_signal(old_bit), log_signal(new_bit));
-
-						tmp_sig[i] = new_bit;
-					}
-					c->setPort(conn.first, tmp_sig);
+				for (int i = 0; i < GetSize(old_sig); i++)
+					if (primary_inputs.check(old_sig[i]))
+						new_sig[i] = old_sig[i];
+				if (old_sig != new_sig) {
+					log("Changing input %s of cell %s (%s): %s -> %s\n",
+							log_id(conn.first), log_id(c), log_id(c->type),
+							log_signal(old_sig), log_signal(new_sig));
+					c->setPort(conn.first, new_sig);
 				}
 			}
 
@@ -432,57 +414,6 @@ struct EquivMakeWorker
 		}
 	}
 
-	void init_bit2driven()
-	{
-		for (auto cell : equiv_mod->cells()) {
-			if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
-				continue;
-			for (auto &conn : cell->connections())
-			{
-				if (yosys_celltypes.cell_input(cell->type, conn.first))
-					for (auto bit : assign_map(conn.second))
-					{
-						bit2driven[bit].insert(cell);
-					}
-			}
-		}
-	}
-
-	bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
-	{
-		if (source_bit == target_bit)
-			return true;
-
-		if (bit2driven.count(source_bit) == 0)
-			return false;
-
-		auto driven_cells = bit2driven.at(source_bit);
-		for (auto driven_cell: driven_cells)
-		{
-			bool is_comb = comb_ct.cell_known(driven_cell->type);
-			if (!is_comb)
-				continue;
-
-			if (visited_cells.count(driven_cell) > 0)
-				continue;
-			visited_cells.insert(driven_cell);
-
-			for (auto &conn: driven_cell->connections())
-			{
-				if (yosys_celltypes.cell_input(driven_cell->type, conn.first))
-					continue;
-
-				for (auto bit: conn.second) {
-					bool is_in_fanout = check_signal_in_fanout(visited_cells, bit, target_bit);
-					if (is_in_fanout == true)
-						return true;
-				}
-			}
-		}
-
-		return false;
-	}
-
 	void run()
 	{
 		copy_to_equiv();