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-rw-r--r--passes/cmds/blackbox.cc2
-rw-r--r--passes/cmds/bugpoint.cc90
-rw-r--r--passes/cmds/setundef.cc118
-rw-r--r--passes/cmds/stat.cc33
-rw-r--r--passes/cmds/tee.cc5
-rw-r--r--passes/cmds/write_file.cc2
6 files changed, 211 insertions, 39 deletions
diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
index 6094f8f16..d09ed872e 100644
--- a/passes/cmds/blackbox.cc
+++ b/passes/cmds/blackbox.cc
@@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct BlackboxPass : public Pass {
- BlackboxPass() : Pass("blackbox", "change type of cells in the design") { }
+ BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index 038ab7c7c..5a47988ec 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -51,14 +51,14 @@ struct BugpointPass : public Pass {
log(" only consider crashes that place this string in the log file.\n");
log("\n");
log(" -fast\n");
- log(" run `clean -purge` after each minimization step. converges faster, but\n");
- log(" produces larger testcases, and may fail to produce any testcase at all if\n");
- log(" the crash is related to dangling wires.\n");
+ log(" run `proc_clean; clean -purge` after each minimization step. converges\n");
+ log(" faster, but produces larger testcases, and may fail to produce any\n");
+ log(" testcase at all if the crash is related to dangling wires.\n");
log("\n");
log(" -clean\n");
- log(" run `clean -purge` before checking testcase and after finishing. produces\n");
- log(" smaller and more useful testcases, but may fail to produce any testcase\n");
- log(" at all if the crash is related to dangling wires.\n");
+ log(" run `proc_clean; clean -purge` before checking testcase and after\n");
+ log(" finishing. produces smaller and more useful testcases, but may fail to\n");
+ log(" produce any testcase at all if the crash is related to dangling wires.\n");
log("\n");
log(" -modules\n");
log(" try to remove modules.\n");
@@ -72,6 +72,12 @@ struct BugpointPass : public Pass {
log(" -connections\n");
log(" try to reconnect ports to 'x.\n");
log("\n");
+ log(" -assigns\n");
+ log(" try to remove process assigns from cases.\n");
+ log("\n");
+ log(" -updates\n");
+ log(" try to remove process updates from syncs.\n");
+ log("\n");
}
bool run_yosys(RTLIL::Design *design, string yosys_cmd, string script)
@@ -110,6 +116,7 @@ struct BugpointPass : public Pass {
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto &it : design->modules_)
design_copy->add(it.second->clone());
+ Pass::call(design_copy, "proc_clean -quiet");
Pass::call(design_copy, "clean -purge");
if (do_delete)
@@ -117,7 +124,7 @@ struct BugpointPass : public Pass {
return design_copy;
}
- RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections)
+ RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections, bool assigns, bool updates)
{
RTLIL::Design *design_copy = new RTLIL::Design;
for (auto &it : design->modules_)
@@ -225,6 +232,59 @@ struct BugpointPass : public Pass {
}
}
}
+ if (assigns)
+ {
+ for (auto mod : design_copy->modules())
+ {
+ if (mod->get_blackbox_attribute())
+ continue;
+
+ for (auto &pr : mod->processes)
+ {
+ vector<RTLIL::CaseRule*> cases = {&pr.second->root_case};
+ while (!cases.empty())
+ {
+ RTLIL::CaseRule *cs = cases[0];
+ cases.erase(cases.begin());
+ for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it)
+ {
+ if (index++ == seed)
+ {
+ log("Trying to remove assign %s %s in %s.%s.\n", log_signal((*it).first), log_signal((*it).second), mod->name.c_str(), pr.first.c_str());
+ cs->actions.erase(it);
+ return design_copy;
+ }
+ }
+ for (auto &sw : cs->switches)
+ cases.insert(cases.end(), sw->cases.begin(), sw->cases.end());
+ }
+ }
+ }
+ }
+ if (updates)
+ {
+ for (auto mod : design_copy->modules())
+ {
+ if (mod->get_blackbox_attribute())
+ continue;
+
+ for (auto &pr : mod->processes)
+ {
+ for (auto &sy : pr.second->syncs)
+ {
+ for (auto it = sy->actions.begin(); it != sy->actions.end(); ++it)
+ {
+ if (index++ == seed)
+ {
+ log("Trying to remove sync %s update %s %s in %s.%s.\n", log_signal(sy->signal), log_signal((*it).first), log_signal((*it).second), mod->name.c_str(), pr.first.c_str());
+ sy->actions.erase(it);
+ return design_copy;
+ }
+ }
+ }
+ }
+ }
+ }
return NULL;
}
@@ -232,7 +292,7 @@ struct BugpointPass : public Pass {
{
string yosys_cmd = "yosys", script, grep;
bool fast = false, clean = false;
- bool modules = false, ports = false, cells = false, connections = false, has_part = false;
+ bool modules = false, ports = false, cells = false, connections = false, assigns = false, updates = false, has_part = false;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -277,6 +337,16 @@ struct BugpointPass : public Pass {
has_part = true;
continue;
}
+ if (args[argidx] == "-assigns") {
+ assigns = true;
+ has_part = true;
+ continue;
+ }
+ if (args[argidx] == "-updates") {
+ updates = true;
+ has_part = true;
+ continue;
+ }
break;
}
extra_args(args, argidx, design);
@@ -290,6 +360,8 @@ struct BugpointPass : public Pass {
ports = true;
cells = true;
connections = true;
+ assigns = true;
+ updates = true;
}
if (!design->full_selection())
@@ -305,7 +377,7 @@ struct BugpointPass : public Pass {
bool found_something = false, stage2 = false;
while (true)
{
- if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections))
+ if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections, assigns, updates))
{
simplified = clean_design(simplified, fast, /*do_delete=*/true);
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index f6949c820..3eedc86b8 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -393,44 +393,112 @@ struct SetundefPass : public Pass {
ffbits.insert(bit);
}
- for (auto wire : module->wires())
+ auto process_initwires = [&]()
{
- if (!wire->attributes.count("\\init"))
- continue;
+ dict<Wire*, int> wire_weights;
- for (auto bit : sigmap(wire))
- ffbits.erase(bit);
+ for (auto wire : initwires)
+ {
+ int weight = 0;
- initwires.insert(wire);
- }
+ for (auto bit : sigmap(wire))
+ weight += ffbits.count(bit) ? +1 : -1;
+
+ wire_weights[wire] = weight;
+ }
+
+ initwires.sort([&](Wire *a, Wire *b) { return wire_weights.at(a) > wire_weights.at(b); });
+
+ for (auto wire : initwires)
+ {
+ Const &initval = wire->attributes["\\init"];
+ initval.bits.resize(GetSize(wire), State::Sx);
+
+ for (int i = 0; i < GetSize(wire); i++) {
+ SigBit bit = sigmap(SigBit(wire, i));
+ if (initval[i] == State::Sx && ffbits.count(bit)) {
+ initval[i] = worker.next_bit();
+ ffbits.erase(bit);
+ }
+ }
+
+ if (initval.is_fully_undef())
+ wire->attributes.erase("\\init");
+ }
+
+ initwires.clear();
+ };
for (int wire_types = 0; wire_types < 2; wire_types++)
- for (auto wire : module->wires())
+ {
+ // prioritize wires that already have an init attribute
+ if (!ffbits.empty())
{
- if (wire->name[0] == (wire_types ? '\\' : '$'))
- next_wire:
- continue;
+ for (auto wire : module->wires())
+ {
+ if (wire->name[0] == (wire_types ? '\\' : '$'))
+ continue;
- for (auto bit : sigmap(wire))
- if (!ffbits.count(bit))
- goto next_wire;
+ if (!wire->attributes.count("\\init"))
+ continue;
- for (auto bit : sigmap(wire))
- ffbits.erase(bit);
+ Const &initval = wire->attributes["\\init"];
+ initval.bits.resize(GetSize(wire), State::Sx);
+
+ if (initval.is_fully_undef()) {
+ wire->attributes.erase("\\init");
+ continue;
+ }
- initwires.insert(wire);
+ for (int i = 0; i < GetSize(wire); i++)
+ if (initval[i] != State::Sx)
+ ffbits.erase(sigmap(SigBit(wire, i)));
+
+ initwires.insert(wire);
+ }
+
+ process_initwires();
}
- for (auto wire : initwires)
- {
- Const &initval = wire->attributes["\\init"];
+ // next consider wires that completely contain bits to be initialized
+ if (!ffbits.empty())
+ {
+ for (auto wire : module->wires())
+ {
+ if (wire->name[0] == (wire_types ? '\\' : '$'))
+ continue;
- for (int i = 0; i < GetSize(wire); i++)
- if (GetSize(initval) <= i)
- initval.bits.push_back(worker.next_bit());
- else if (initval.bits[i] == State::Sx)
- initval.bits[i] = worker.next_bit();
+ for (auto bit : sigmap(wire))
+ if (!ffbits.count(bit))
+ goto next_wire;
+
+ initwires.insert(wire);
+
+ next_wire:
+ continue;
+ }
+
+ process_initwires();
+ }
+
+ // finally use whatever wire we can find.
+ if (!ffbits.empty())
+ {
+ for (auto wire : module->wires())
+ {
+ if (wire->name[0] == (wire_types ? '\\' : '$'))
+ continue;
+
+ for (auto bit : sigmap(wire))
+ if (ffbits.count(bit))
+ initwires.insert(wire);
+ }
+
+ process_initwires();
+ }
}
+
+ log_assert(ffbits.empty());
}
module->rewrite_sigspecs(worker);
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index d22685b62..80b400e0c 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -223,6 +223,33 @@ struct statdata_t
log("\n");
log(" Estimated number of LCs: %10d\n", lc_cnt);
}
+
+ if (tech == "cmos")
+ {
+ int tran_cnt = 0;
+ bool tran_cnt_exact = true;
+
+ for (auto it : num_cells_by_type) {
+ auto ctype = it.first;
+ auto cnum = it.second;
+
+ if (ctype == "$_NOT_")
+ tran_cnt += 2*cnum;
+ else if (ctype.in("$_NAND_", "$_NOR_"))
+ tran_cnt += 4*cnum;
+ else if (ctype.in("$_AOI3_", "$_OAI3_"))
+ tran_cnt += 6*cnum;
+ else if (ctype.in("$_AOI4_", "$_OAI4_"))
+ tran_cnt += 8*cnum;
+ else if (ctype.in("$_DFF_P_", "$_DFF_N_"))
+ tran_cnt += 16*cnum;
+ else
+ tran_cnt_exact = false;
+ }
+
+ log("\n");
+ log(" Estimated number of transistors: %10d%s\n", tran_cnt, tran_cnt_exact ? "" : "+");
+ }
}
};
@@ -285,8 +312,8 @@ struct StatPass : public Pass {
log(" use cell area information from the provided liberty file\n");
log("\n");
log(" -tech <technology>\n");
- log(" print area estemate for the specified technology. Corrently supported\n");
- log(" calues for <technology>: xilinx\n");
+ log(" print area estemate for the specified technology. Currently supported\n");
+ log(" values for <technology>: xilinx, cmos\n");
log("\n");
log(" -width\n");
log(" annotate internal cell types with their word width.\n");
@@ -330,7 +357,7 @@ struct StatPass : public Pass {
}
extra_args(args, argidx, design);
- if (techname != "" && techname != "xilinx")
+ if (techname != "" && techname != "xilinx" && techname != "cmos")
log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
for (auto mod : design->selected_modules())
diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc
index ee96ace86..1a44bdaec 100644
--- a/passes/cmds/tee.cc
+++ b/passes/cmds/tee.cc
@@ -52,7 +52,9 @@ struct TeePass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
std::vector<FILE*> backup_log_files, files_to_close;
+ std::vector<std::ostream*> backup_log_streams;
int backup_log_verbose_level = log_verbose_level;
+ backup_log_streams = log_streams;
backup_log_files = log_files;
size_t argidx;
@@ -60,6 +62,7 @@ struct TeePass : public Pass {
{
if (args[argidx] == "-q" && files_to_close.empty()) {
log_files.clear();
+ log_streams.clear();
continue;
}
if ((args[argidx] == "-o" || args[argidx] == "-a") && argidx+1 < args.size()) {
@@ -89,6 +92,7 @@ struct TeePass : public Pass {
for (auto cf : files_to_close)
fclose(cf);
log_files = backup_log_files;
+ log_streams = backup_log_streams;
throw;
}
@@ -97,6 +101,7 @@ struct TeePass : public Pass {
log_verbose_level = backup_log_verbose_level;
log_files = backup_log_files;
+ log_streams = backup_log_streams;
}
} TeePass;
diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc
index 9613b462b..64a762d7c 100644
--- a/passes/cmds/write_file.cc
+++ b/passes/cmds/write_file.cc
@@ -62,7 +62,7 @@ struct WriteFileFrontend : public Frontend {
if (argidx < args.size() && args[argidx].rfind("-", 0) != 0)
output_filename = args[argidx++];
else
- log_cmd_error("Missing putput filename.\n");
+ log_cmd_error("Missing output filename.\n");
extra_args(f, filename, args, argidx);
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-30 02:52:12 +0000