2 files changed, 63 insertions, 2 deletions

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index a582de56d..519dce452 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -69,17 +69,30 @@ struct RenamePass : public Pass {
 		log("Assign short auto-generated names to all selected wires and cells with private\n");
 		log("names.\n");
 		log("\n");
+		log("    rename -hide [selection]\n");
+		log("\n");
+		log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
+		log("with public names. This ignores all selected ports.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
 		bool flag_enumerate = false;
+		bool flag_hide = false;
+		bool got_mode = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
 			std::string arg = args[argidx];
-			if (arg == "-enumerate") {
+			if (arg == "-enumerate" && !got_mode) {
 				flag_enumerate = true;
+				got_mode = true;
+				continue;
+			}
+			if (arg == "-hide" && !got_mode) {
+				flag_hide = true;
+				got_mode = true;
 				continue;
 			}
 			break;
@@ -117,6 +130,36 @@ struct RenamePass : public Pass {
 			}
 		}
 		else
+		if (flag_hide)
+		{
+			extra_args(args, argidx, design);
+
+			for (auto &mod : design->modules)
+			{
+				RTLIL::Module *module = mod.second;
+				if (!design->selected(module))
+					continue;
+
+				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+				for (auto &it : module->wires) {
+					if (design->selected(module, it.second))
+						if (it.first[0] == '\\' && it.second->port_id == 0)
+							it.second->name = NEW_ID;
+					new_wires[it.second->name] = it.second;
+				}
+				module->wires.swap(new_wires);
+
+				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				for (auto &it : module->cells) {
+					if (design->selected(module, it.second))
+						if (it.first[0] == '\\')
+							it.second->name = NEW_ID;
+					new_cells[it.second->name] = it.second;
+				}
+				module->cells.swap(new_cells);
+			}
+		}
+		else
 		{
 			if (argidx+2 != args.size())
 				log_cmd_error("Invalid number of arguments!\n");
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 137f8618a..ec560772e 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -272,6 +272,21 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 			if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
 				selected_wires.insert(it.second);
 
+		for (auto &conn : mod->connections)
+		{
+			std::vector<RTLIL::SigBit> conn_lhs = conn.first.to_sigbit_vector();
+			std::vector<RTLIL::SigBit> conn_rhs = conn.second.to_sigbit_vector();
+
+			for (size_t i = 0; i < conn_lhs.size(); i++) {
+				if (conn_lhs[i].wire == NULL || conn_rhs[i].wire == NULL)
+					continue;
+				if (mode != 'i' && selected_wires.count(conn_rhs[i].wire) && lhs.selected_members[mod->name].count(conn_lhs[i].wire->name) == 0)
+					lhs.selected_members[mod->name].insert(conn_lhs[i].wire->name), sel_objects++, max_objects--;
+				if (mode != 'o' && selected_wires.count(conn_lhs[i].wire) && lhs.selected_members[mod->name].count(conn_rhs[i].wire->name) == 0)
+					lhs.selected_members[mod->name].insert(conn_rhs[i].wire->name), sel_objects++, max_objects--;
+			}
+		}
+
 		for (auto &cell : mod->cells)
 		for (auto &conn : cell.second->connections)
 		{
@@ -514,7 +529,10 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 	} else {
 		size_t pos = arg.find('/');
 		if (pos == std::string::npos) {
-			arg_mod = arg;
+			if (arg.find(':') == std::string::npos)
+				arg_mod = arg;
+			else
+				arg_mod = "*", arg_memb = arg;
 		} else {
 			arg_mod = arg.substr(0, pos);
 			arg_memb = arg.substr(pos+1);