diff options
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/cellaigs.cc | 30 | ||||
-rw-r--r-- | kernel/celledges.cc | 84 | ||||
-rw-r--r-- | kernel/celltypes.h | 177 | ||||
-rw-r--r-- | kernel/consteval.h | 36 | ||||
-rw-r--r-- | kernel/constids.inc | 200 | ||||
-rw-r--r-- | kernel/macc.h | 12 | ||||
-rw-r--r-- | kernel/rtlil.cc | 820 | ||||
-rw-r--r-- | kernel/satgen.h | 112 | ||||
-rw-r--r-- | kernel/timinginfo.h | 26 | ||||
-rw-r--r-- | kernel/yosys.h | 4 |
10 files changed, 822 insertions, 679 deletions
diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 02854edb2..2c82b1bca 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -268,9 +268,9 @@ Aig::Aig(Cell *cell) cell->parameters.sort(); for (auto p : cell->parameters) { - if (p.first == ID(A_WIDTH) && mkname_a_signed) { + if (p.first == ID::A_WIDTH && mkname_a_signed) { name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); - } else if (p.first == ID(B_WIDTH) && mkname_b_signed) { + } else if (p.first == ID::B_WIDTH && mkname_b_signed) { name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); } else { mkname_last = name; @@ -280,11 +280,11 @@ Aig::Aig(Cell *cell) mkname_a_signed = false; mkname_b_signed = false; mkname_is_signed = false; - if (p.first == ID(A_SIGNED)) { + if (p.first == ID::A_SIGNED) { mkname_a_signed = true; mkname_is_signed = p.second.as_bool(); } - if (p.first == ID(B_SIGNED)) { + if (p.first == ID::B_SIGNED) { mkname_b_signed = true; mkname_is_signed = p.second.as_bool(); } @@ -320,7 +320,7 @@ Aig::Aig(Cell *cell) if (cell->type.in(ID($mux), ID($_MUX_))) { - int S = mk.inport(ID(S)); + int S = mk.inport(ID::S); for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { int A = mk.inport(ID::A, i); int B = mk.inport(ID::B, i); @@ -390,8 +390,8 @@ Aig::Aig(Cell *cell) int width = GetSize(cell->getPort(ID::Y)); vector<int> A = mk.inport_vec(ID::A, width); vector<int> B = mk.inport_vec(ID::B, width); - int carry = mk.inport(ID(CI)); - int binv = mk.inport(ID(BI)); + int carry = mk.inport(ID::CI); + int binv = mk.inport(ID::BI); for (auto &n : B) n = mk.xor_gate(n, binv); vector<int> X(width), CO(width); @@ -399,8 +399,8 @@ Aig::Aig(Cell *cell) for (int i = 0; i < width; i++) X[i] = mk.xor_gate(A[i], B[i]); mk.outport_vec(Y, ID::Y); - mk.outport_vec(X, ID(X)); - mk.outport_vec(CO, ID(CO)); + mk.outport_vec(X, ID::X); + mk.outport_vec(CO, ID::CO); goto optimize; } @@ -422,7 +422,7 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); + int C = mk.inport(ID::C); int Y = mk.nor_gate(mk.and_gate(A, B), C); mk.outport(Y, ID::Y); goto optimize; @@ -432,7 +432,7 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); + int C = mk.inport(ID::C); int Y = mk.nand_gate(mk.or_gate(A, B), C); mk.outport(Y, ID::Y); goto optimize; @@ -442,8 +442,8 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); - int D = mk.inport(ID(D)); + int C = mk.inport(ID::C); + int D = mk.inport(ID::D); int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D)); mk.outport(Y, ID::Y); goto optimize; @@ -453,8 +453,8 @@ Aig::Aig(Cell *cell) { int A = mk.inport(ID::A); int B = mk.inport(ID::B); - int C = mk.inport(ID(C)); - int D = mk.inport(ID(D)); + int C = mk.inport(ID::C); + int D = mk.inport(ID::D); int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); mk.outport(Y, ID::Y); goto optimize; diff --git a/kernel/celledges.cc b/kernel/celledges.cc index d0bb99e83..54e0168e2 100644 --- a/kernel/celledges.cc +++ b/kernel/celledges.cc @@ -24,29 +24,25 @@ PRIVATE_NAMESPACE_BEGIN void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int y_width = GetSize(cell->getPort(ID::Y)); for (int i = 0; i < y_width; i++) { if (i < a_width) - db->add_edge(cell, A, i, Y, i, -1); + db->add_edge(cell, ID::A, i, ID::Y, i, -1); else if (is_signed && a_width > 0) - db->add_edge(cell, A, a_width-1, Y, i, -1); + db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1); } } void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int y_width = GetSize(cell->getPort(ID::Y)); if (cell->type == ID($and) && !is_signed) { if (a_width > b_width) @@ -58,41 +54,37 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int i = 0; i < y_width; i++) { if (i < a_width) - db->add_edge(cell, A, i, Y, i, -1); + db->add_edge(cell, ID::A, i, ID::Y, i, -1); else if (is_signed && a_width > 0) - db->add_edge(cell, A, a_width-1, Y, i, -1); + db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1); if (i < b_width) - db->add_edge(cell, B, i, Y, i, -1); + db->add_edge(cell, ID::B, i, ID::Y, i, -1); else if (is_signed && b_width > 0) - db->add_edge(cell, B, b_width-1, Y, i, -1); + db->add_edge(cell, ID::B, b_width-1, ID::Y, i, -1); } } void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int y_width = GetSize(cell->getPort(ID::Y)); if (is_signed && a_width == 1) y_width = std::min(y_width, 1); for (int i = 0; i < y_width; i++) for (int k = 0; k <= i && k < a_width; k++) - db->add_edge(cell, A, k, Y, i, -1); + db->add_edge(cell, ID::A, k, ID::Y, i, -1); } void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, Y = ID::Y; - - bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); - int y_width = GetSize(cell->getPort(Y)); + bool is_signed = cell->getParam(ID::A_SIGNED).as_bool(); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int y_width = GetSize(cell->getPort(ID::Y)); if (!is_signed && cell->type != ID($sub)) { int ab_width = std::max(a_width, b_width); @@ -104,55 +96,49 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) for (int k = 0; k <= i; k++) { if (k < a_width) - db->add_edge(cell, A, k, Y, i, -1); + db->add_edge(cell, ID::A, k, ID::Y, i, -1); if (k < b_width) - db->add_edge(cell, B, k, Y, i, -1); + db->add_edge(cell, ID::B, k, ID::Y, i, -1); } } } void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, Y = ID::Y; - - int a_width = GetSize(cell->getPort(A)); + int a_width = GetSize(cell->getPort(ID::A)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, A, i, Y, 0, -1); + db->add_edge(cell, ID::A, i, ID::Y, 0, -1); } void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, Y = ID::Y; - - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); for (int i = 0; i < a_width; i++) - db->add_edge(cell, A, i, Y, 0, -1); + db->add_edge(cell, ID::A, i, ID::Y, 0, -1); for (int i = 0; i < b_width; i++) - db->add_edge(cell, B, i, Y, 0, -1); + db->add_edge(cell, ID::B, i, ID::Y, 0, -1); } void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) { - IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; - - int a_width = GetSize(cell->getPort(A)); - int b_width = GetSize(cell->getPort(B)); - int s_width = GetSize(cell->getPort(S)); + int a_width = GetSize(cell->getPort(ID::A)); + int b_width = GetSize(cell->getPort(ID::B)); + int s_width = GetSize(cell->getPort(ID::S)); for (int i = 0; i < a_width; i++) { - db->add_edge(cell, A, i, Y, i, -1); + db->add_edge(cell, ID::A, i, ID::Y, i, -1); for (int k = i; k < b_width; k += a_width) - db->add_edge(cell, B, k, Y, i, -1); + db->add_edge(cell, ID::B, k, ID::Y, i, -1); for (int k = 0; k < s_width; k++) - db->add_edge(cell, S, k, Y, i, -1); + db->add_edge(cell, ID::S, k, ID::Y, i, -1); } } diff --git a/kernel/celltypes.h b/kernel/celltypes.h index bc96fd602..450865ce9 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -84,26 +84,22 @@ struct CellTypes { setup_internals_eval(); - IdString A = ID::A, B = ID::B, EN = ID(EN), Y = ID::Y; - IdString SRC = ID(SRC), DST = ID(DST), DAT = ID(DAT); - IdString EN_SRC = ID(EN_SRC), EN_DST = ID(EN_DST); - - setup_type(ID($tribuf), {A, EN}, {Y}, true); - - setup_type(ID($assert), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($assume), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($live), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($fair), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($cover), {A, EN}, pool<RTLIL::IdString>(), true); - setup_type(ID($initstate), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($anyconst), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($anyseq), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($allconst), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($allseq), pool<RTLIL::IdString>(), {Y}, true); - setup_type(ID($equiv), {A, B}, {Y}, true); - setup_type(ID($specify2), {EN, SRC, DST}, pool<RTLIL::IdString>(), true); - setup_type(ID($specify3), {EN, SRC, DST, DAT}, pool<RTLIL::IdString>(), true); - setup_type(ID($specrule), {EN_SRC, EN_DST, SRC, DST}, pool<RTLIL::IdString>(), true); + setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true); + + setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true); + setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true); + setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true); + setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true); + setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true); } void setup_internals_eval() @@ -121,134 +117,109 @@ struct CellTypes ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($logic_and), ID($logic_or), ID($concat), ID($macc) }; - IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; - IdString P = ID(P), G = ID(G), C = ID(C), X = ID(X); - IdString BI = ID(BI), CI = ID(CI), CO = ID(CO), EN = ID(EN); for (auto type : unary_ops) - setup_type(type, {A}, {Y}, true); + setup_type(type, {ID::A}, {ID::Y}, true); for (auto type : binary_ops) - setup_type(type, {A, B}, {Y}, true); + setup_type(type, {ID::A, ID::B}, {ID::Y}, true); for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)})) - setup_type(type, {A, B, S}, {Y}, true); + setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true); - setup_type(ID($lcu), {P, G, CI}, {CO}, true); - setup_type(ID($alu), {A, B, CI, BI}, {X, Y, CO}, true); - setup_type(ID($fa), {A, B, C}, {X, Y}, true); + setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true); + setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true); + setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true); } void setup_internals_ff() { - IdString SET = ID(SET), CLR = ID(CLR), CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); - IdString Q = ID(Q), D = ID(D); - - setup_type(ID($sr), {SET, CLR}, {Q}); - setup_type(ID($ff), {D}, {Q}); - setup_type(ID($dff), {CLK, D}, {Q}); - setup_type(ID($dffe), {CLK, EN, D}, {Q}); - setup_type(ID($dffsr), {CLK, SET, CLR, D}, {Q}); - setup_type(ID($adff), {CLK, ARST, D}, {Q}); - setup_type(ID($dlatch), {EN, D}, {Q}); - setup_type(ID($dlatchsr), {EN, SET, CLR, D}, {Q}); - + setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q}); + setup_type(ID($ff), {ID::D}, {ID::Q}); + setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q}); + setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q}); + setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q}); + setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q}); + setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q}); + setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q}); } void setup_internals_mem() { setup_internals_ff(); - IdString CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); - IdString ADDR = ID(ADDR), DATA = ID(DATA), RD_EN = ID(RD_EN); - IdString RD_CLK = ID(RD_CLK), RD_ADDR = ID(RD_ADDR), WR_CLK = ID(WR_CLK), WR_EN = ID(WR_EN); - IdString WR_ADDR = ID(WR_ADDR), WR_DATA = ID(WR_DATA), RD_DATA = ID(RD_DATA); - IdString CTRL_IN = ID(CTRL_IN), CTRL_OUT = ID(CTRL_OUT); - - setup_type(ID($memrd), {CLK, EN, ADDR}, {DATA}); - setup_type(ID($memwr), {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>()); - setup_type(ID($meminit), {ADDR, DATA}, pool<RTLIL::IdString>()); - setup_type(ID($mem), {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA}); + setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA}); + setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>()); + setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>()); + setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA}); - setup_type(ID($fsm), {CLK, ARST, CTRL_IN}, {CTRL_OUT}); + setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT}); } void setup_stdcells() { setup_stdcells_eval(); - IdString A = ID::A, E = ID(E), Y = ID::Y; - - setup_type(ID($_TBUF_), {A, E}, {Y}, true); + setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true); } void setup_stdcells_eval() { - IdString A = ID::A, B = ID::B, C = ID(C), D = ID(D); - IdString E = ID(E), F = ID(F), G = ID(G), H = ID(H); - IdString I = ID(I), J = ID(J), K = ID(K), L = ID(L); - IdString M = ID(M), N = ID(N), O = ID(O), P = ID(P); - IdString S = ID(S), T = ID(T), U = ID(U), V = ID(V); - IdString Y = ID::Y; - - setup_type(ID($_BUF_), {A}, {Y}, true); - setup_type(ID($_NOT_), {A}, {Y}, true); - setup_type(ID($_AND_), {A, B}, {Y}, true); - setup_type(ID($_NAND_), {A, B}, {Y}, true); - setup_type(ID($_OR_), {A, B}, {Y}, true); - setup_type(ID($_NOR_), {A, B}, {Y}, true); - setup_type(ID($_XOR_), {A, B}, {Y}, true); - setup_type(ID($_XNOR_), {A, B}, {Y}, true); - setup_type(ID($_ANDNOT_), {A, B}, {Y}, true); - setup_type(ID($_ORNOT_), {A, B}, {Y}, true); - setup_type(ID($_MUX_), {A, B, S}, {Y}, true); - setup_type(ID($_NMUX_), {A, B, S}, {Y}, true); - setup_type(ID($_MUX4_), {A, B, C, D, S, T}, {Y}, true); - setup_type(ID($_MUX8_), {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true); - setup_type(ID($_MUX16_), {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true); - setup_type(ID($_AOI3_), {A, B, C}, {Y}, true); - setup_type(ID($_OAI3_), {A, B, C}, {Y}, true); - setup_type(ID($_AOI4_), {A, B, C, D}, {Y}, true); - setup_type(ID($_OAI4_), {A, B, C, D}, {Y}, true); + setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true); + setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true); + setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true); + setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true); + setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true); + setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true); + setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true); + setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true); + setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true); + setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true); + setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true); + setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true); } void setup_stdcells_mem() { - IdString S = ID(S), R = ID(R), C = ID(C); - IdString D = ID(D), Q = ID(Q), E = ID(E); - std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'}; for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q}); + setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q}); - setup_type(ID($_FF_), {D}, {Q}); + setup_type(ID($_FF_), {ID::D}, {ID::Q}); for (auto c1 : list_np) - setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q}); + setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) - setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q}); + setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_01) - setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q}); + setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q}); + setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q}); for (auto c1 : list_np) - setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q}); + setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q}); for (auto c1 : list_np) for (auto c2 : list_np) for (auto c3 : list_np) - setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q}); + setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q}); } void clear() @@ -300,7 +271,7 @@ struct CellTypes signed1 = false, signed2 = false; } -#define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len); +#define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len); HANDLE_CELL_TYPE(not) HANDLE_CELL_TYPE(and) HANDLE_CELL_TYPE(or) @@ -371,8 +342,8 @@ struct CellTypes { if (cell->type == ID($slice)) { RTLIL::Const ret; - int width = cell->parameters.at(ID(Y_WIDTH)).as_int(); - int offset = cell->parameters.at(ID(OFFSET)).as_int(); + int width = cell->parameters.at(ID::Y_WIDTH).as_int(); + int offset = cell->parameters.at(ID::OFFSET).as_int(); ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width); return ret; } @@ -385,9 +356,9 @@ struct CellTypes if (cell->type == ID($lut)) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); + int width = cell->parameters.at(ID::WIDTH).as_int(); - std::vector<RTLIL::State> t = cell->parameters.at(ID(LUT)).bits; + std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits; while (GetSize(t) < (1 << width)) t.push_back(State::S0); t.resize(1 << width); @@ -411,9 +382,9 @@ struct CellTypes if (cell->type == ID($sop)) { - int width = cell->parameters.at(ID(WIDTH)).as_int(); - int depth = cell->parameters.at(ID(DEPTH)).as_int(); - std::vector<RTLIL::State> t = cell->parameters.at(ID(TABLE)).bits; + int width = cell->parameters.at(ID::WIDTH).as_int(); + int depth = cell->parameters.at(ID::DEPTH).as_int(); + std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits; while (GetSize(t) < width*depth*2) t.push_back(State::S0); @@ -447,9 +418,9 @@ struct CellTypes return default_ret; } - bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); - bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); - int result_len = cell->parameters.count(ID(Y_WIDTH)) > 0 ? cell->parameters[ID(Y_WIDTH)].as_int() : -1; + bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool(); + bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool(); + int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1; return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp); } diff --git a/kernel/consteval.h b/kernel/consteval.h index 7a83d28e7..ff8cf86d6 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -91,10 +91,10 @@ struct ConstEval { if (cell->type == ID($lcu)) { - RTLIL::SigSpec sig_p = cell->getPort(ID(P)); - RTLIL::SigSpec sig_g = cell->getPort(ID(G)); - RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); - RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID(CO)))); + RTLIL::SigSpec sig_p = cell->getPort(ID::P); + RTLIL::SigSpec sig_g = cell->getPort(ID::G); + RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); + RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO))); if (sig_co.is_fully_const()) return true; @@ -133,8 +133,8 @@ struct ConstEval if (sig_y.is_fully_const()) return true; - if (cell->hasPort(ID(S))) { - sig_s = cell->getPort(ID(S)); + if (cell->hasPort(ID::S)) { + sig_s = cell->getPort(ID::S); if (!eval(sig_s, undef, cell)) return false; } @@ -200,8 +200,8 @@ struct ConstEval } else if (cell->type == ID($fa)) { - RTLIL::SigSpec sig_c = cell->getPort(ID(C)); - RTLIL::SigSpec sig_x = cell->getPort(ID(X)); + RTLIL::SigSpec sig_c = cell->getPort(ID::C); + RTLIL::SigSpec sig_x = cell->getPort(ID::X); int width = GetSize(sig_c); if (!eval(sig_a, undef, cell)) @@ -229,11 +229,11 @@ struct ConstEval } else if (cell->type == ID($alu)) { - bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); - bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); + bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool(); + bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool(); - RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); - RTLIL::SigSpec sig_bi = cell->getPort(ID(BI)); + RTLIL::SigSpec sig_ci = cell->getPort(ID::CI); + RTLIL::SigSpec sig_bi = cell->getPort(ID::BI); if (!eval(sig_a, undef, cell)) return false; @@ -247,8 +247,8 @@ struct ConstEval if (!eval(sig_bi, undef, cell)) return false; - RTLIL::SigSpec sig_x = cell->getPort(ID(X)); - RTLIL::SigSpec sig_co = cell->getPort(ID(CO)); + RTLIL::SigSpec sig_x = cell->getPort(ID::X); + RTLIL::SigSpec sig_co = cell->getPort(ID::CO); bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); sig_a.extend_u0(GetSize(sig_y), signed_a); @@ -309,10 +309,10 @@ struct ConstEval RTLIL::SigSpec sig_c, sig_d; if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { - if (cell->hasPort(ID(C))) - sig_c = cell->getPort(ID(C)); - if (cell->hasPort(ID(D))) - sig_d = cell->getPort(ID(D)); + if (cell->hasPort(ID::C)) + sig_c = cell->getPort(ID::C); + if (cell->hasPort(ID::D)) + sig_d = cell->getPort(ID::D); } if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) diff --git a/kernel/constids.inc b/kernel/constids.inc index 18be12229..68a5782fd 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -1,27 +1,213 @@ X(A) -X(B) -X(S) -X(Y) -X(keep) -X(src) -X(whitebox) -X(blackbox) +X(abc9_box) +X(abc9_box_id) +X(abc9_box_seq) +X(abc9_carry) +X(abc9_flop) +X(abc9_holes) +X(abc9_init) +X(abc9_lut) +X(abc9_mergeability) +X(abc9_scc) +X(abc9_scc_id) +X(abcgroup) +X(ABITS) +X(ADDR) X(allconst) X(allseq) +X(always_comb) +X(always_ff) +X(always_latch) X(anyconst) X(anyseq) +X(ARST) +X(ARST_POLARITY) +X(ARST_VALUE) +X(A_SIGNED) +X(A_WIDTH) +X(B) +X(BI) +X(blackbox) +X(B_SIGNED) +X(B_WIDTH) +X(C) +X(cells_not_processed) +X(CFG_ABITS) +X(CFG_DBITS) +X(CFG_INIT) +X(CI) +X(CLK) +X(clkbuf_driver) +X(clkbuf_inhibit) +X(clkbuf_inv) +X(clkbuf_sink) +X(CLK_ENABLE) +X(CLK_POLARITY) +X(CLR) +X(CLR_POLARITY) +X(CO) +X(CONFIG) +X(CONFIG_WIDTH) +X(CTRL_IN) +X(CTRL_IN_WIDTH) +X(CTRL_OUT) +X(CTRL_OUT_WIDTH) +X(D) +X(DAT) +X(DATA) +X(DAT_DST_PEN) +X(DAT_DST_POL) X(defaultvalue) +X(DELAY) +X(DEPTH) +X(DST) +X(DST_EN) +X(DST_PEN) +X(DST_POL) +X(DST_WIDTH) +X(dynports) +X(E) +X(EDGE_EN) +X(EDGE_POL) +X(EN) +X(EN_DST) +X(EN_POLARITY) +X(EN_SRC) +X(equiv_merged) +X(equiv_region) +X(extract_order) +X(F) X(fsm_encoding) +X(fsm_export) +X(FULL) X(full_case) +X(G) X(gclk) +X(gentb_clock) +X(gentb_constant) +X(gentb_skip) +X(H) +X(hdlname) +X(hierconn) +X(I) +X(INIT) +X(init) X(initial_top) +X(interface_modport) +X(interfaces_replaced_in_module) +X(interface_type) +X(invertible_pin) +X(iopad_external_pin) X(is_interface) +X(J) +X(K) +X(keep) +X(keep_hierarchy) +X(L) +X(lib_whitebox) +X(localparam) +X(LUT) +X(lut_keep) +X(M) +X(maximize) X(mem2reg) +X(MEMID) +X(minimize) +X(module_not_derived) +X(N) +X(NAME) X(noblackbox) X(nolatches) +X(nomem2init) X(nomem2reg) +X(nomeminit) X(nosync) +X(O) +X(OFFSET) +X(onehot) +X(P) X(parallel_case) +X(parameter) +X(PRIORITY) +X(Q) +X(qwp_position) +X(R) +X(RD_ADDR) +X(RD_CLK) +X(RD_CLK_ENABLE) +X(RD_CLK_POLARITY) +X(RD_DATA) +X(RD_EN) +X(RD_PORTS) +X(RD_TRANSPARENT) +X(reg) +X(S) +X(SET) +X(SET_POLARITY) +X(SIZE) +X(SRC) +X(src) +X(SRC_DST_PEN) +X(SRC_DST_POL) +X(SRC_EN) +X(SRC_PEN) +X(SRC_POL) +X(SRC_WIDTH) +X(STATE_BITS) +X(STATE_NUM) +X(STATE_NUM_LOG2) +X(STATE_RST) +X(STATE_TABLE) +X(submod) +X(S_WIDTH) +X(T) +X(TABLE) +X(techmap_autopurge) +X(_TECHMAP_BITS_CONNMAP_) +X(_TECHMAP_CELLTYPE_) +X(techmap_celltype) +X(techmap_maccmap) +X(_TECHMAP_REPLACE_) +X(techmap_simplemap) +X(_techmap_special_) +X(techmap_wrap) +X(T_FALL_MAX) +X(T_FALL_MIN) +X(T_FALL_TYP) +X(T_LIMIT) +X(T_LIMIT2) +X(T_LIMIT2_MAX) +X(T_LIMIT2_MIN) +X(T_LIMIT2_TYP) +X(T_LIMIT_MAX) +X(T_LIMIT_MIN) +X(T_LIMIT_TYP) +X(to_delete) X(top) +X(TRANS_NUM) +X(TRANSPARENT) +X(TRANS_TABLE) +X(T_RISE_MAX) +X(T_RISE_MIN) +X(T_RISE_TYP) +X(TYPE) +X(U) +X(unique) +X(unused_bits) +X(V) X(wand) +X(whitebox) +X(WIDTH) +X(wildcard_port_conns) X(wor) +X(WORDS) +X(WR_ADDR) +X(WR_CLK) +X(WR_CLK_ENABLE) +X(WR_CLK_POLARITY) +X(WR_DATA) +X(WR_EN) +X(WR_PORTS) +X(X) +X(Y) +X(Y_WIDTH) diff --git a/kernel/macc.h b/kernel/macc.h index 371f6737d..e9f6f05e9 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -104,11 +104,11 @@ struct Macc ports.clear(); bit_ports = cell->getPort(ID::B); - std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits; + std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits; int config_cursor = 0; #ifndef NDEBUG - int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int(); + int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int(); log_assert(GetSize(config_bits) >= config_width); #endif @@ -193,10 +193,10 @@ struct Macc cell->setPort(ID::A, port_a); cell->setPort(ID::B, bit_ports); - cell->setParam(ID(CONFIG), config_bits); - cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); - cell->setParam(ID(A_WIDTH), GetSize(port_a)); - cell->setParam(ID(B_WIDTH), GetSize(bit_ports)); + cell->setParam(ID::CONFIG, config_bits); + cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits)); + cell->setParam(ID::A_WIDTH, GetSize(port_a)); + cell->setParam(ID::B_WIDTH, GetSize(bit_ports)); } bool eval(RTLIL::Const &result) const diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 83e324535..00c116115 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -273,15 +273,15 @@ pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const void RTLIL::AttrObject::set_src_attribute(const std::string &src) { if (src.empty()) - attributes.erase(ID(src)); + attributes.erase(ID::src); else - attributes[ID(src)] = src; + attributes[ID::src] = src; } std::string RTLIL::AttrObject::get_src_attribute() const { std::string src; - const auto it = attributes.find(ID(src)); + const auto it = attributes.find(ID::src); if (it != attributes.end()) src = it->second.decode_string(); return src; @@ -428,7 +428,7 @@ RTLIL::Module *RTLIL::Design::top_module() int module_count = 0; for (auto mod : selected_modules()) { - if (mod->get_bool_attribute(ID(top))) + if (mod->get_bool_attribute(ID::top)) return mod; module_count++; module = mod; @@ -823,9 +823,9 @@ namespace { error(__LINE__); if (check_matched_sign) { - log_assert(expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) != 0); - bool a_is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool(); - bool b_is_signed = cell->parameters.at(ID(B_SIGNED)).as_bool(); + log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0); + bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool(); + bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool(); if (a_is_signed != b_is_signed) error(__LINE__); } @@ -838,357 +838,357 @@ namespace { return; if (cell->type.in(ID($not), ID($pos), ID($neg))) { - param_bool(ID(A_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); return; } if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(true); return; } if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) { - param_bool(ID(A_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); return; } if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED), /*expected=*/false); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED, /*expected=*/false); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } if (cell->type.in(ID($shift), ID($shiftx))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(true); return; } if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(cell->type != ID($pow)); return; } if (cell->type == ID($fa)) { - port(ID::A, param(ID(WIDTH))); - port(ID::B, param(ID(WIDTH))); - port(ID(C), param(ID(WIDTH))); - port(ID(X), param(ID(WIDTH))); - port(ID::Y, param(ID(WIDTH))); + port(ID::A, param(ID::WIDTH)); + port(ID::B, param(ID::WIDTH)); + port(ID::C, param(ID::WIDTH)); + port(ID::X, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($lcu)) { - port(ID(P), param(ID(WIDTH))); - port(ID(G), param(ID(WIDTH))); - port(ID(CI), 1); - port(ID(CO), param(ID(WIDTH))); + port(ID::P, param(ID::WIDTH)); + port(ID::G, param(ID::WIDTH)); + port(ID::CI, 1); + port(ID::CO, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($alu)) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID(CI), 1); - port(ID(BI), 1); - port(ID(X), param(ID(Y_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); - port(ID(CO), param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::CI, 1); + port(ID::BI, 1); + port(ID::X, param(ID::Y_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); + port(ID::CO, param(ID::Y_WIDTH)); check_expected(true); return; } if (cell->type == ID($macc)) { - param(ID(CONFIG)); - param(ID(CONFIG_WIDTH)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param(ID::CONFIG); + param(ID::CONFIG_WIDTH); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); Macc().from_cell(cell); return; } if (cell->type == ID($logic_not)) { - param_bool(ID(A_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(); return; } if (cell->type.in(ID($logic_and), ID($logic_or))) { - param_bool(ID(A_SIGNED)); - param_bool(ID(B_SIGNED)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); + param_bool(ID::A_SIGNED); + param_bool(ID::B_SIGNED); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); check_expected(/*check_matched_sign=*/false); return; } if (cell->type == ID($slice)) { - param(ID(OFFSET)); - port(ID::A, param(ID(A_WIDTH))); - port(ID::Y, param(ID(Y_WIDTH))); - if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH))) + param(ID::OFFSET); + port(ID::A, param(ID::A_WIDTH)); + port(ID::Y, param(ID::Y_WIDTH)); + if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH)) error(__LINE__); check_expected(); return; } if (cell->type == ID($concat)) { - port(ID::A, param(ID(A_WIDTH))); - port(ID::B, param(ID(B_WIDTH))); - port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH))); + port(ID::A, param(ID::A_WIDTH)); + port(ID::B, param(ID::B_WIDTH)); + port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH)); check_expected(); return; } if (cell->type == ID($mux)) { - port(ID::A, param(ID(WIDTH))); - port(ID::B, param(ID(WIDTH))); - port(ID(S), 1); - port(ID::Y, param(ID(WIDTH))); + port(ID::A, param(ID::WIDTH)); + port(ID::B, param(ID::WIDTH)); + port(ID::S, 1); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($pmux)) { - port(ID::A, param(ID(WIDTH))); - port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH))); - port(ID(S), param(ID(S_WIDTH))); - port(ID::Y, param(ID(WIDTH))); + port(ID::A, param(ID::WIDTH)); + port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH)); + port(ID::S, param(ID::S_WIDTH)); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($lut)) { - param(ID(LUT)); - port(ID::A, param(ID(WIDTH))); + param(ID::LUT); + port(ID::A, param(ID::WIDTH)); port(ID::Y, 1); check_expected(); return; } if (cell->type == ID($sop)) { - param(ID(DEPTH)); - param(ID(TABLE)); - port(ID::A, param(ID(WIDTH))); + param(ID::DEPTH); + param(ID::TABLE); + port(ID::A, param(ID::WIDTH)); port(ID::Y, 1); check_expected(); return; } if (cell->type == ID($sr)) { - param_bool(ID(SET_POLARITY)); - param_bool(ID(CLR_POLARITY)); - port(ID(SET), param(ID(WIDTH))); - port(ID(CLR), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::SET_POLARITY); + param_bool(ID::CLR_POLARITY); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($ff)) { - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dff)) { - param_bool(ID(CLK_POLARITY)); - port(ID(CLK), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + port(ID::CLK, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dffe)) { - param_bool(ID(CLK_POLARITY)); - param_bool(ID(EN_POLARITY)); - port(ID(CLK), 1); - port(ID(EN), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + param_bool(ID::EN_POLARITY); + port(ID::CLK, 1); + port(ID::EN, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dffsr)) { - param_bool(ID(CLK_POLARITY)); - param_bool(ID(SET_POLARITY)); - param_bool(ID(CLR_POLARITY)); - port(ID(CLK), 1); - port(ID(SET), param(ID(WIDTH))); - port(ID(CLR), param(ID(WIDTH))); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + param_bool(ID::SET_POLARITY); + param_bool(ID::CLR_POLARITY); + port(ID::CLK, 1); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($adff)) { - param_bool(ID(CLK_POLARITY)); - param_bool(ID(ARST_POLARITY)); - param_bits(ID(ARST_VALUE), param(ID(WIDTH))); - port(ID(CLK), 1); - port(ID(ARST), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::CLK_POLARITY); + param_bool(ID::ARST_POLARITY); + param_bits(ID::ARST_VALUE, param(ID::WIDTH)); + port(ID::CLK, 1); + port(ID::ARST, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dlatch)) { - param_bool(ID(EN_POLARITY)); - port(ID(EN), 1); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::EN_POLARITY); + port(ID::EN, 1); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($dlatchsr)) { - param_bool(ID(EN_POLARITY)); - param_bool(ID(SET_POLARITY)); - param_bool(ID(CLR_POLARITY)); - port(ID(EN), 1); - port(ID(SET), param(ID(WIDTH))); - port(ID(CLR), param(ID(WIDTH))); - port(ID(D), param(ID(WIDTH))); - port(ID(Q), param(ID(WIDTH))); + param_bool(ID::EN_POLARITY); + param_bool(ID::SET_POLARITY); + param_bool(ID::CLR_POLARITY); + port(ID::EN, 1); + port(ID::SET, param(ID::WIDTH)); + port(ID::CLR, param(ID::WIDTH)); + port(ID::D, param(ID::WIDTH)); + port(ID::Q, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($fsm)) { - param(ID(NAME)); - param_bool(ID(CLK_POLARITY)); - param_bool(ID(ARST_POLARITY)); - param(ID(STATE_BITS)); - param(ID(STATE_NUM)); - param(ID(STATE_NUM_LOG2)); - param(ID(STATE_RST)); - param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM))); - param(ID(TRANS_NUM)); - param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH)))); - port(ID(CLK), 1); - port(ID(ARST), 1); - port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH))); - port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH))); + param(ID::NAME); + param_bool(ID::CLK_POLARITY); + param_bool(ID::ARST_POLARITY); + param(ID::STATE_BITS); + param(ID::STATE_NUM); + param(ID::STATE_NUM_LOG2); + param(ID::STATE_RST); + param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM)); + param(ID::TRANS_NUM); + param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH))); + port(ID::CLK, 1); + port(ID::ARST, 1); + port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH)); + port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH)); check_expected(); return; } if (cell->type == ID($memrd)) { - param(ID(MEMID)); - param_bool(ID(CLK_ENABLE)); - param_bool(ID(CLK_POLARITY)); - param_bool(ID(TRANSPARENT)); - port(ID(CLK), 1); - port(ID(EN), 1); - port(ID(ADDR), param(ID(ABITS))); - port(ID(DATA), param(ID(WIDTH))); + param(ID::MEMID); + param_bool(ID::CLK_ENABLE); + param_bool(ID::CLK_POLARITY); + param_bool(ID::TRANSPARENT); + port(ID::CLK, 1); + port(ID::EN, 1); + port(ID::ADDR, param(ID::ABITS)); + port(ID::DATA, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($memwr)) { - param(ID(MEMID)); - param_bool(ID(CLK_ENABLE)); - param_bool(ID(CLK_POLARITY)); - param(ID(PRIORITY)); - port(ID(CLK), 1); - port(ID(EN), param(ID(WIDTH))); - port(ID(ADDR), param(ID(ABITS))); - port(ID(DATA), param(ID(WIDTH))); + param(ID::MEMID); + param_bool(ID::CLK_ENABLE); + param_bool(ID::CLK_POLARITY); + param(ID::PRIORITY); + port(ID::CLK, 1); + port(ID::EN, param(ID::WIDTH)); + port(ID::ADDR, param(ID::ABITS)); + port(ID::DATA, param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($meminit)) { - param(ID(MEMID)); - param(ID(PRIORITY)); - port(ID(ADDR), param(ID(ABITS))); - port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS))); + param(ID::MEMID); + param(ID::PRIORITY); + port(ID::ADDR, param(ID::ABITS)); + port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS)); check_expected(); return; } if (cell->type == ID($mem)) { - param(ID(MEMID)); - param(ID(SIZE)); - param(ID(OFFSET)); - param(ID(INIT)); - param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS)))); - param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS)))); - param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS)))); - param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS)))); - param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS)))); - port(ID(RD_CLK), param(ID(RD_PORTS))); - port(ID(RD_EN), param(ID(RD_PORTS))); - port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS))); - port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH))); - port(ID(WR_CLK), param(ID(WR_PORTS))); - port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH))); - port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS))); - port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH))); + param(ID::MEMID); + param(ID::SIZE); + param(ID::OFFSET); + param(ID::INIT); + param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS))); + param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS))); + param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS))); + param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS))); + param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS))); + port(ID::RD_CLK, param(ID::RD_PORTS)); + port(ID::RD_EN, param(ID::RD_PORTS)); + port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS)); + port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH)); + port(ID::WR_CLK, param(ID::WR_PORTS)); + port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH)); + port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS)); + port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH)); check_expected(); return; } if (cell->type == ID($tribuf)) { - port(ID::A, param(ID(WIDTH))); - port(ID::Y, param(ID(WIDTH))); - port(ID(EN), 1); + port(ID::A, param(ID::WIDTH)); + port(ID::Y, param(ID::WIDTH)); + port(ID::EN, 1); check_expected(); return; } if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) { port(ID::A, 1); - port(ID(EN), 1); + port(ID::EN, 1); check_expected(); return; } @@ -1200,7 +1200,7 @@ namespace { } if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) { - port(ID::Y, param(ID(WIDTH))); + port(ID::Y, param(ID::WIDTH)); check_expected(); return; } @@ -1214,45 +1214,45 @@ namespace { } if (cell->type.in(ID($specify2), ID($specify3))) { - param_bool(ID(FULL)); - param_bool(ID(SRC_DST_PEN)); - param_bool(ID(SRC_DST_POL)); - param(ID(T_RISE_MIN)); - param(ID(T_RISE_TYP)); - param(ID(T_RISE_MAX)); - param(ID(T_FALL_MIN)); - param(ID(T_FALL_TYP)); - param(ID(T_FALL_MAX)); - port(ID(EN), 1); - port(ID(SRC), param(ID(SRC_WIDTH))); - port(ID(DST), param(ID(DST_WIDTH))); + param_bool(ID::FULL); + param_bool(ID::SRC_DST_PEN); + param_bool(ID::SRC_DST_POL); + param(ID::T_RISE_MIN); + param(ID::T_RISE_TYP); + param(ID::T_RISE_MAX); + param(ID::T_FALL_MIN); + param(ID::T_FALL_TYP); + param(ID::T_FALL_MAX); + port(ID::EN, 1); + port(ID::SRC, param(ID::SRC_WIDTH)); + port(ID::DST, param(ID::DST_WIDTH)); if (cell->type == ID($specify3)) { - param_bool(ID(EDGE_EN)); - param_bool(ID(EDGE_POL)); - param_bool(ID(DAT_DST_PEN)); - param_bool(ID(DAT_DST_POL)); - port(ID(DAT), param(ID(DST_WIDTH))); + param_bool(ID::EDGE_EN); + param_bool(ID::EDGE_POL); + param_bool(ID::DAT_DST_PEN); + param_bool(ID::DAT_DST_POL); + port(ID::DAT, param(ID::DST_WIDTH)); } check_expected(); return; } if (cell->type == ID($specrule)) { - param(ID(TYPE)); - param_bool(ID(SRC_PEN)); - param_bool(ID(SRC_POL)); - param_bool(ID(DST_PEN)); - param_bool(ID(DST_POL)); - param(ID(T_LIMIT_MIN)); - param(ID(T_LIMIT_TYP)); - param(ID(T_LIMIT_MAX)); - param(ID(T_LIMIT2_MIN)); - param(ID(T_LIMIT2_TYP)); - param(ID(T_LIMIT2_MAX)); - port(ID(SRC_EN), 1); - port(ID(DST_EN), 1); - port(ID(SRC), param(ID(SRC_WIDTH))); - port(ID(DST), param(ID(DST_WIDTH))); + param(ID::TYPE); + param_bool(ID::SRC_PEN); + param_bool(ID::SRC_POL); + param_bool(ID::DST_PEN); + param_bool(ID::DST_POL); + param(ID::T_LIMIT_MIN); + param(ID::T_LIMIT_TYP); + param(ID::T_LIMIT_MAX); + param(ID::T_LIMIT2_MIN); + param(ID::T_LIMIT2_TYP); + param(ID::T_LIMIT2_MAX); + port(ID::SRC_EN, 1); + port(ID::DST_EN, 1); + port(ID::SRC, param(ID::SRC_WIDTH)); + port(ID::DST, param(ID::DST_WIDTH)); check_expected(); return; } @@ -1267,62 +1267,62 @@ namespace { if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; } - - if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID(E),1); check_expected(); return; } - - if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(S),1); port(ID(T),1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID::Y,1); check_expected(); return; } - if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(I),1); port(ID(J),1); port(ID(K),1); port(ID(L),1); port(ID(M),1); port(ID(N),1); port(ID(O),1); port(ID(P),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID(V),1); port(ID::Y,1); check_expected(); return; } - - if (cell->type == ID($_SR_NN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_SR_NP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_SR_PN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_SR_PP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; } - - if (cell->type == ID($_FF_)) { port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFF_N_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; } - if (cell->type == ID($_DFF_P_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; } - - if (cell->type == ID($_DFFE_NN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; } - if (cell->type == ID($_DFFE_NP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; } - if (cell->type == ID($_DFFE_PN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; } - if (cell->type == ID($_DFFE_PP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; } - - if (cell->type == ID($_DFF_NN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - if (cell->type == ID($_DFF_NN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - if (cell->type == ID($_DFF_NP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - if (cell->type == ID($_DFF_NP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - if (cell->type == ID($_DFF_PN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - if (cell->type == ID($_DFF_PN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - if (cell->type == ID($_DFF_PP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - if (cell->type == ID($_DFF_PP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; } - - if (cell->type == ID($_DFFSR_NNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFFSR_NNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFFSR_NPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFFSR_NPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFFSR_PNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFFSR_PNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFFSR_PPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DFFSR_PPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - - if (cell->type == ID($_DLATCH_N_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCH_P_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - - if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } - if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; } + if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; } + + if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; } + + if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; } + if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; } + + if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; } + + if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; } + if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; } + + if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; } + + if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; } + + if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + + if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + + if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } + if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } error(__LINE__); } @@ -1831,9 +1831,9 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(A_SIGNED)] = is_signed; \ - cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->parameters[ID::A_SIGNED] = is_signed; \ + cell->parameters[ID::A_WIDTH] = sig_a.size(); \ + cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ @@ -1858,11 +1858,11 @@ DEF_METHOD(LogicNot, 1, ID($logic_not)) #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(A_SIGNED)] = is_signed; \ - cell->parameters[ID(B_SIGNED)] = is_signed; \ - cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ - cell->parameters[ID(B_WIDTH)] = sig_b.size(); \ - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->parameters[ID::A_SIGNED] = is_signed; \ + cell->parameters[ID::B_SIGNED] = is_signed; \ + cell->parameters[ID::A_WIDTH] = sig_a.size(); \ + cell->parameters[ID::B_WIDTH] = sig_b.size(); \ + cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::B, sig_b); \ cell->setPort(ID::Y, sig_y); \ @@ -1900,11 +1900,11 @@ DEF_METHOD(LogicOr, 1, ID($logic_or)) #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(A_SIGNED)] = is_signed; \ - cell->parameters[ID(B_SIGNED)] = false; \ - cell->parameters[ID(A_WIDTH)] = sig_a.size(); \ - cell->parameters[ID(B_WIDTH)] = sig_b.size(); \ - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \ + cell->parameters[ID::A_SIGNED] = is_signed; \ + cell->parameters[ID::B_SIGNED] = false; \ + cell->parameters[ID::A_WIDTH] = sig_a.size(); \ + cell->parameters[ID::B_WIDTH] = sig_b.size(); \ + cell->parameters[ID::Y_WIDTH] = sig_y.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::B, sig_b); \ cell->setPort(ID::Y, sig_y); \ @@ -1925,11 +1925,11 @@ DEF_METHOD(Sshr, sig_a.size(), ID($sshr)) #define DEF_METHOD(_func, _type, _pmux) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ - cell->parameters[ID(WIDTH)] = sig_a.size(); \ - if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \ + cell->parameters[ID::WIDTH] = sig_a.size(); \ + if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \ cell->setPort(ID::A, sig_a); \ cell->setPort(ID::B, sig_b); \ - cell->setPort(ID(S), sig_s); \ + cell->setPort(ID::S, sig_s); \ cell->setPort(ID::Y, sig_y); \ cell->set_src_attribute(src); \ return cell; \ @@ -2025,11 +2025,11 @@ DEF_METHOD_5(Oai4Gate, ID($_OAI4_), A, B, C, D, Y) RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($pow)); - cell->parameters[ID(A_SIGNED)] = a_signed; - cell->parameters[ID(B_SIGNED)] = b_signed; - cell->parameters[ID(A_WIDTH)] = sig_a.size(); - cell->parameters[ID(B_WIDTH)] = sig_b.size(); - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); + cell->parameters[ID::A_SIGNED] = a_signed; + cell->parameters[ID::B_SIGNED] = b_signed; + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::B_WIDTH] = sig_b.size(); + cell->parameters[ID::Y_WIDTH] = sig_y.size(); cell->setPort(ID::A, sig_a); cell->setPort(ID::B, sig_b); cell->setPort(ID::Y, sig_y); @@ -2040,9 +2040,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &s RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($slice)); - cell->parameters[ID(A_WIDTH)] = sig_a.size(); - cell->parameters[ID(Y_WIDTH)] = sig_y.size(); - cell->parameters[ID(OFFSET)] = offset; + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::Y_WIDTH] = sig_y.size(); + cell->parameters[ID::OFFSET] = offset; cell->setPort(ID::A, sig_a); cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); @@ -2052,8 +2052,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($concat)); - cell->parameters[ID(A_WIDTH)] = sig_a.size(); - cell->parameters[ID(B_WIDTH)] = sig_b.size(); + cell->parameters[ID::A_WIDTH] = sig_a.size(); + cell->parameters[ID::B_WIDTH] = sig_b.size(); cell->setPort(ID::A, sig_a); cell->setPort(ID::B, sig_b); cell->setPort(ID::Y, sig_y); @@ -2064,8 +2064,8 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($lut)); - cell->parameters[ID(LUT)] = lut; - cell->parameters[ID(WIDTH)] = sig_a.size(); + cell->parameters[ID::LUT] = lut; + cell->parameters[ID::WIDTH] = sig_a.size(); cell->setPort(ID::A, sig_a); cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); @@ -2075,9 +2075,9 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &s RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($tribuf)); - cell->parameters[ID(WIDTH)] = sig_a.size(); + cell->parameters[ID::WIDTH] = sig_a.size(); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->setPort(ID::Y, sig_y); cell->set_src_attribute(src); return cell; @@ -2087,7 +2087,7 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, const RTLIL::SigSpec { RTLIL::Cell *cell = addCell(name, ID($assert)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } @@ -2096,7 +2096,7 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, const RTLIL::SigSpec { RTLIL::Cell *cell = addCell(name, ID($assume)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } @@ -2105,7 +2105,7 @@ RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, const RTLIL::SigSpec & { RTLIL::Cell *cell = addCell(name, ID($live)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } @@ -2114,7 +2114,7 @@ RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, const RTLIL::SigSpec & { RTLIL::Cell *cell = addCell(name, ID($fair)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } @@ -2123,7 +2123,7 @@ RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, const RTLIL::SigSpec { RTLIL::Cell *cell = addCell(name, ID($cover)); cell->setPort(ID::A, sig_a); - cell->setPort(ID(EN), sig_en); + cell->setPort(ID::EN, sig_en); cell->set_src_attribute(src); return cell; } @@ -2141,12 +2141,12 @@ RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, const RTLIL::SigSpec RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($sr)); - cell->parameters[ID(SET_POLARITY)] = set_polarity; - cell->parameters[ID(CLR_POLARITY)] = clr_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(SET), sig_set); - cell->setPort(ID(CLR), sig_clr); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::SET_POLARITY] = set_polarity; + cell->parameters[ID::CLR_POLARITY] = clr_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::SET, sig_set); + cell->setPort(ID::CLR, sig_clr); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2154,9 +2154,9 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &si RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($ff)); - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2164,11 +2164,11 @@ RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &si RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dff)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2176,13 +2176,13 @@ RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &s RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dffe)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(EN_POLARITY)] = en_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(EN), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::EN_POLARITY] = en_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::EN, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2191,15 +2191,15 @@ RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, const RTLIL::SigSpec RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dffsr)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(SET_POLARITY)] = set_polarity; - cell->parameters[ID(CLR_POLARITY)] = clr_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(SET), sig_set); - cell->setPort(ID(CLR), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::SET_POLARITY] = set_polarity; + cell->parameters[ID::CLR_POLARITY] = clr_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::SET, sig_set); + cell->setPort(ID::CLR, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2208,14 +2208,14 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec & RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($adff)); - cell->parameters[ID(CLK_POLARITY)] = clk_polarity; - cell->parameters[ID(ARST_POLARITY)] = arst_polarity; - cell->parameters[ID(ARST_VALUE)] = arst_value; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(CLK), sig_clk); - cell->setPort(ID(ARST), sig_arst); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::CLK_POLARITY] = clk_polarity; + cell->parameters[ID::ARST_POLARITY] = arst_polarity; + cell->parameters[ID::ARST_VALUE] = arst_value; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::CLK, sig_clk); + cell->setPort(ID::ARST, sig_arst); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2223,11 +2223,11 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, const RTLIL::SigSpec & RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dlatch)); - cell->parameters[ID(EN_POLARITY)] = en_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(EN), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::EN_POLARITY] = en_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::EN, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2236,15 +2236,15 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSp RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($dlatchsr)); - cell->parameters[ID(EN_POLARITY)] = en_polarity; - cell->parameters[ID(SET_POLARITY)] = set_polarity; - cell->parameters[ID(CLR_POLARITY)] = clr_polarity; - cell->parameters[ID(WIDTH)] = sig_q.size(); - cell->setPort(ID(EN), sig_en); - cell->setPort(ID(SET), sig_set); - cell->setPort(ID(CLR), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->parameters[ID::EN_POLARITY] = en_polarity; + cell->parameters[ID::SET_POLARITY] = set_polarity; + cell->parameters[ID::CLR_POLARITY] = clr_polarity; + cell->parameters[ID::WIDTH] = sig_q.size(); + cell->setPort(ID::EN, sig_en); + cell->setPort(ID::SET, sig_set); + cell->setPort(ID::CLR, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2252,8 +2252,8 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, const RTLIL::SigSp RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src) { RTLIL::Cell *cell = addCell(name, ID($_FF_)); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2261,9 +2261,9 @@ RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2271,10 +2271,10 @@ RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpe RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(E), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::E, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2283,11 +2283,11 @@ RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, const RTLIL::SigS RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(S), sig_set); - cell->setPort(ID(R), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::S, sig_set); + cell->setPort(ID::R, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2296,10 +2296,10 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSp bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0')); - cell->setPort(ID(C), sig_clk); - cell->setPort(ID(R), sig_arst); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::C, sig_clk); + cell->setPort(ID::R, sig_arst); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2307,9 +2307,9 @@ RTLIL::Cell* RTLIL::Module::addAdffGate(RTLIL::IdString name, const RTLIL::SigSp RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N')); - cell->setPort(ID(E), sig_en); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::E, sig_en); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2318,11 +2318,11 @@ RTLIL::Cell* RTLIL::Module::addDlatchsrGate(RTLIL::IdString name, const RTLIL::S RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src) { RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N')); - cell->setPort(ID(E), sig_en); - cell->setPort(ID(S), sig_set); - cell->setPort(ID(R), sig_clr); - cell->setPort(ID(D), sig_d); - cell->setPort(ID(Q), sig_q); + cell->setPort(ID::E, sig_en); + cell->setPort(ID::S, sig_set); + cell->setPort(ID::R, sig_clr); + cell->setPort(ID::D, sig_d); + cell->setPort(ID::Q, sig_q); cell->set_src_attribute(src); return cell; } @@ -2331,7 +2331,7 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const st { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($anyconst)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2341,7 +2341,7 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std: { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($anyseq)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2351,7 +2351,7 @@ RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const st { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($allconst)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2361,7 +2361,7 @@ RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std: { RTLIL::SigSpec sig = addWire(NEW_ID, width); Cell *cell = addCell(name, ID($allseq)); - cell->setParam(ID(WIDTH), width); + cell->setParam(ID::WIDTH, width); cell->setPort(ID::Y, sig); cell->set_src_attribute(src); return sig; @@ -2588,25 +2588,25 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; if (type == ID($mux) || type == ID($pmux)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]); + parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); if (type == ID($pmux)) - parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]); + parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]); check(); return; } if (type == ID($lut) || type == ID($sop)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID::A]); + parameters[ID::WIDTH] = GetSize(connections_[ID::A]); return; } if (type == ID($fa)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]); + parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); return; } if (type == ID($lcu)) { - parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]); + parameters[ID::WIDTH] = GetSize(connections_[ID::CO]); return; } @@ -2615,28 +2615,28 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) if (connections_.count(ID::A)) { if (signedness_ab) { if (set_a_signed) - parameters[ID(A_SIGNED)] = true; - else if (parameters.count(ID(A_SIGNED)) == 0) - parameters[ID(A_SIGNED)] = false; + parameters[ID::A_SIGNED] = true; + else if (parameters.count(ID::A_SIGNED) == 0) + parameters[ID::A_SIGNED] = false; } - parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]); + parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]); } if (connections_.count(ID::B)) { if (signedness_ab) { if (set_b_signed) - parameters[ID(B_SIGNED)] = true; - else if (parameters.count(ID(B_SIGNED)) == 0) - parameters[ID(B_SIGNED)] = false; + parameters[ID::B_SIGNED] = true; + else if (parameters.count(ID::B_SIGNED) == 0) + parameters[ID::B_SIGNED] = false; } - parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]); + parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]); } if (connections_.count(ID::Y)) - parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]); + parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]); - if (connections_.count(ID(Q))) - parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]); + if (connections_.count(ID::Q)) + parameters[ID::WIDTH] = GetSize(connections_[ID::Q]); check(); } diff --git a/kernel/satgen.h b/kernel/satgen.h index 133389eee..88b84b7e6 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -224,8 +224,8 @@ struct SatGen void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false) { bool is_signed = forced_signed; - if (!forced_signed && cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters.count(ID(B_SIGNED)) > 0) - is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); + if (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0) + is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool(); while (vec_a.size() < vec_b.size() || vec_a.size() < y_width) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_b.size() < vec_a.size() || vec_b.size() < y_width) @@ -241,7 +241,7 @@ struct SatGen void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false) { - bool is_signed = forced_signed || (cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool()); + bool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool()); while (vec_a.size() < vec_y.size()) vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); while (vec_y.size() < vec_a.size()) @@ -397,8 +397,8 @@ struct SatGen int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0); int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0); - int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0); - int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0); + int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0); + int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0); int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); int yy = model_undef ? ez->literal() : y; @@ -411,8 +411,8 @@ struct SatGen { int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0); int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0); - int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0); - int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0); + int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0); + int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0); int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0); if (aoi_mode) @@ -479,7 +479,7 @@ struct SatGen { std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; @@ -492,7 +492,7 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b)); @@ -508,7 +508,7 @@ struct SatGen { std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; @@ -524,7 +524,7 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); + std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); int maybe_a = ez->CONST_TRUE; @@ -684,7 +684,7 @@ struct SatGen if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) { - bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); + bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool(); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); @@ -774,7 +774,7 @@ struct SatGen int extend_bit = ez->CONST_FALSE; - if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) + if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool()) extend_bit = a.back(); while (y.size() < a.size()) @@ -792,10 +792,10 @@ struct SatGen shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($sshr)) - shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); + shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type.in(ID($shift), ID($shiftx))) - shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); + shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); ez->assume(ez->vec_eq(shifted_a, yy)); @@ -807,7 +807,7 @@ struct SatGen std::vector<int> undef_a_shifted; extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE; - if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) + if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool()) extend_bit = undef_a.back(); while (undef_y.size() < undef_a.size()) @@ -822,13 +822,13 @@ struct SatGen undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($sshr)) - undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE); + undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($shift)) - undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); if (cell->type == ID($shiftx)) - undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE); + undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b); @@ -945,7 +945,7 @@ struct SatGen std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> a_u, b_u; - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) { a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a); b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b); } else { @@ -971,12 +971,12 @@ struct SatGen std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size()); if (cell->type == ID($div)) { - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u))); else ez->assume(ez->vec_eq(y_tmp, y_u)); } else { - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf))); else ez->assume(ez->vec_eq(y_tmp, chain_buf)); @@ -987,7 +987,7 @@ struct SatGen } else { std::vector<int> div_zero_result; if (cell->type == ID($div)) { - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) { std::vector<int> all_ones(y.size(), ez->CONST_TRUE); std::vector<int> only_first_one(y.size(), ez->CONST_FALSE); only_first_one.at(0) = ez->CONST_TRUE; @@ -999,7 +999,7 @@ struct SatGen } else { int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size()); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); - if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) + if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); else div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE); @@ -1021,7 +1021,7 @@ struct SatGen std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> lut; - for (auto bit : cell->getParam(ID(LUT)).bits) + for (auto bit : cell->getParam(ID::LUT).bits) lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); while (GetSize(lut) < (1 << GetSize(a))) lut.push_back(ez->CONST_FALSE); @@ -1070,10 +1070,10 @@ struct SatGen std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); - int width = cell->getParam(ID(WIDTH)).as_int(); - int depth = cell->getParam(ID(DEPTH)).as_int(); + int width = cell->getParam(ID::WIDTH).as_int(); + int depth = cell->getParam(ID::DEPTH).as_int(); - vector<State> table_raw = cell->getParam(ID(TABLE)).bits; + vector<State> table_raw = cell->getParam(ID::TABLE).bits; while (GetSize(table_raw) < 2*width*depth) table_raw.push_back(State::S0); @@ -1151,9 +1151,9 @@ struct SatGen { std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> c = importDefSigSpec(cell->getPort(ID(C)), timestep); + std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep); + std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep); std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x; @@ -1169,10 +1169,10 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep); + std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); + std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); ez->assume(ez->vec_eq(undef_x, undef_y)); @@ -1185,10 +1185,10 @@ struct SatGen if (cell->type == ID($lcu)) { - std::vector<int> p = importDefSigSpec(cell->getPort(ID(P)), timestep); - std::vector<int> g = importDefSigSpec(cell->getPort(ID(G)), timestep); - std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep); + std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep); + std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep); std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co; @@ -1197,10 +1197,10 @@ struct SatGen if (model_undef) { - std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID(P)), timestep); - std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID(G)), timestep); - std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep); + std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep); + std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep); int undef_any_p = ez->expression(ezSAT::OpOr, undef_p); int undef_any_g = ez->expression(ezSAT::OpOr, undef_g); @@ -1220,10 +1220,10 @@ struct SatGen std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep); - std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> bi = importDefSigSpec(cell->getPort(ID(BI)), timestep); - std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep); + std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep); + std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep); extendSignalWidth(a, b, y, cell); extendSignalWidth(a, b, x, cell); @@ -1250,12 +1250,12 @@ struct SatGen { std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); - std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); - std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep); + std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep); + std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); - std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); - std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); + std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep); + std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep); extendSignalWidth(undef_a, undef_b, undef_y, cell); extendSignalWidth(undef_a, undef_b, undef_x, cell); @@ -1285,7 +1285,7 @@ struct SatGen { RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec y = cell->getPort(ID::Y); - ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep)); + ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep)); return true; } @@ -1306,20 +1306,20 @@ struct SatGen { if (timestep == 1) { - initial_state.add((*sigmap)(cell->getPort(ID(Q)))); + initial_state.add((*sigmap)(cell->getPort(ID::Q))); } else { - std::vector<int> d = importDefSigSpec(cell->getPort(ID(D)), timestep-1); - std::vector<int> q = importDefSigSpec(cell->getPort(ID(Q)), timestep); + std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1); + std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep); std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q; ez->assume(ez->vec_eq(d, qq)); if (model_undef) { - std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(D)), timestep-1); - std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Q)), timestep); + std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1); + std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep); ez->assume(ez->vec_eq(undef_d, undef_q)); undefGating(q, qq, undef_q); @@ -1397,7 +1397,7 @@ struct SatGen { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); asserts_a[pf].append((*sigmap)(cell->getPort(ID::A))); - asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); + asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN))); return true; } @@ -1405,7 +1405,7 @@ struct SatGen { std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); assumes_a[pf].append((*sigmap)(cell->getPort(ID::A))); - assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); + assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN))); return true; } diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 4b77c02e8..fb4e0930d 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -82,20 +82,20 @@ struct TimingInfo for (auto cell : module->cells()) { if (cell->type == ID($specify2)) { - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); - int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); - int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); + int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); + int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max); if (max < 0) log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell)); - if (cell->getParam(ID(FULL)).as_bool()) { + if (cell->getParam(ID::FULL).as_bool()) { for (const auto &s : src) for (const auto &d : dst) { auto r = t.comb.insert(BitBit(s,d)); @@ -117,16 +117,16 @@ struct TimingInfo } } else if (cell->type == ID($specify3)) { - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); - int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); - int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); + int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); + int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max); if (max < 0) log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); @@ -140,18 +140,18 @@ struct TimingInfo } } else if (cell->type == ID($specrule)) { - auto type = cell->getParam(ID(TYPE)).decode_string(); + auto type = cell->getParam(ID::TYPE).decode_string(); if (type != "$setup" && type != "$setuphold") continue; - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst)); - int max = cell->getParam(ID(T_LIMIT_MAX)).as_int(); + int max = cell->getParam(ID::T_LIMIT_MAX).as_int(); if (max < 0) log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); if (max <= 0) { diff --git a/kernel/yosys.h b/kernel/yosys.h index 179bfe07a..16e0aaf1c 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -306,9 +306,9 @@ RTLIL::IdString new_id(std::string file, int line, std::string func); #define NEW_ID \ YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__) -// Create a statically allocated IdString object, using for example ID(A) or ID($add). +// Create a statically allocated IdString object, using for example ID::A or ID($add). // -// Recipe for Converting old code that is using conversion of strings like "\\A" and +// Recipe for Converting old code that is using conversion of strings like ID::A and // "$add" for creating IdStrings: Run below SED command on the .cc file and then use for // example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary. // |