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-rw-r--r--kernel/register.cc4
-rw-r--r--kernel/register.h2
-rw-r--r--kernel/rtlil.cc2
3 files changed, 5 insertions, 3 deletions
diff --git a/kernel/register.cc b/kernel/register.cc
index 8131fa279..3033ee710 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -612,7 +612,7 @@ void Backend::execute(std::vector<std::string> args, RTLIL::Design *design)
delete f;
}
-void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx)
+void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output)
{
bool called_with_fp = f != NULL;
@@ -647,7 +647,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
#endif
} else {
std::ofstream *ff = new std::ofstream;
- ff->open(filename.c_str(), std::ofstream::trunc);
+ ff->open(filename.c_str(), bin_output ? (std::ofstream::trunc | std::ofstream::binary) : std::ofstream::trunc);
yosys_output_files.insert(filename);
if (ff->fail()) {
delete ff;
diff --git a/kernel/register.h b/kernel/register.h
index c74029823..be836013f 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -109,7 +109,7 @@ struct Backend : Pass
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
- void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx);
+ void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx, bool bin_output = false);
static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::string command);
static void backend_call(RTLIL::Design *design, std::ostream *f, std::string filename, std::vector<std::string> args);
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1d380135b..17be28f78 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT
log_assert(other != NULL);
log_assert(width_ == other->width_);
+ if (rules.empty()) return;
unpack();
other->unpack();
@@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
log_assert(other != NULL);
log_assert(width_ == other->width_);
+ if (rules.empty()) return;
unpack();
other->unpack();