aboutsummaryrefslogtreecommitdiffstats
path: root/frontends
diff options
context:
space:
mode:
Diffstat (limited to 'frontends')
-rw-r--r--frontends/aiger/aigerparse.cc20
-rw-r--r--frontends/ast/simplify.cc8
-rw-r--r--frontends/verific/verific.cc11
-rw-r--r--frontends/verilog/verilog_lexer.l6
-rw-r--r--frontends/verilog/verilog_parser.y49
5 files changed, 75 insertions, 19 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 9d967e6fc..07e3cd6e0 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -69,7 +69,7 @@ struct ConstEvalAig
continue;
for (auto &it2 : it.second->connections())
if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
- auto r YS_ATTRIBUTE(unused) = sig2driver.insert(std::make_pair(it2.second, it.second));
+ auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
log_assert(r.second);
}
}
@@ -400,9 +400,9 @@ void AigerReader::parse_xaiger()
for (int c = f.get(); c != EOF; c = f.get()) {
// XAIGER extensions
if (c == 'm') {
- uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t dataSize = parse_xaiger_literal(f);
uint32_t lutNum = parse_xaiger_literal(f);
- uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t lutSize = parse_xaiger_literal(f);
log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
ConstEvalAig ce(module);
for (unsigned i = 0; i < lutNum; ++i) {
@@ -434,7 +434,7 @@ void AigerReader::parse_xaiger()
int gray = j ^ (j >> 1);
ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
RTLIL::SigBit o(output_sig);
- bool success YS_ATTRIBUTE(unused) = ce.eval(o);
+ bool success = ce.eval(o);
log_assert(success);
log_assert(o.wire == nullptr);
lut_mask[gray] = o.data;
@@ -446,7 +446,7 @@ void AigerReader::parse_xaiger()
}
}
else if (c == 'r') {
- uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_debug("flopNum = %u\n", flopNum);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
@@ -455,7 +455,7 @@ void AigerReader::parse_xaiger()
mergeability.emplace_back(parse_xaiger_literal(f));
}
else if (c == 's') {
- uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t dataSize = parse_xaiger_literal(f);
flopNum = parse_xaiger_literal(f);
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
initial_state.reserve(flopNum);
@@ -469,15 +469,15 @@ void AigerReader::parse_xaiger()
}
else if (c == 'h') {
f.ignore(sizeof(uint32_t));
- uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t version = parse_xaiger_literal(f);
log_assert(version == 1);
- uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t ciNum = parse_xaiger_literal(f);
log_debug("ciNum = %u\n", ciNum);
- uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t coNum = parse_xaiger_literal(f);
log_debug("coNum = %u\n", coNum);
piNum = parse_xaiger_literal(f);
log_debug("piNum = %u\n", piNum);
- uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+ uint32_t poNum = parse_xaiger_literal(f);
log_debug("poNum = %u\n", poNum);
uint32_t boxNum = parse_xaiger_literal(f);
log_debug("boxNum = %u\n", boxNum);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e2da17c09..c4df5c0a0 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -778,7 +778,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
did_something = true;
if (node->type == AST_ENUM) {
- for (auto enode YS_ATTRIBUTE(unused) : node->children){
+ for (auto enode : node->children){
log_assert(enode->type==AST_ENUM_ITEM);
while (node->simplify(true, false, false, 1, -1, false, in_param))
did_something = true;
@@ -1127,6 +1127,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
bool in_param_here = in_param;
if (i == 0 && (type == AST_REPLICATE || type == AST_WIRE))
const_fold_here = true, in_param_here = true;
+ if (i == 0 && (type == AST_GENIF || type == AST_GENCASE))
+ in_param_here = true;
+ if (i == 1 && (type == AST_FOR || type == AST_GENFOR))
+ in_param_here = true;
if (type == AST_PARAMETER || type == AST_LOCALPARAM)
const_fold_here = true;
if (i == 0 && (type == AST_ASSIGN || type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE))
@@ -1943,7 +1947,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
continue;
buf = child->clone();
- while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
+ while (buf->simplify(true, false, false, stage, width_hint, sign_hint, true)) { }
if (buf->type != AST_CONSTANT) {
// for (auto f : log_files)
// dumpAst(f, "verilog-ast> ");
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1630c57bc..9785b8eff 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -53,7 +53,7 @@ USING_YOSYS_NAMESPACE
# error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
#endif
-#if SYMBIOTIC_VERIFIC_API_VERSION < 1
+#if SYMBIOTIC_VERIFIC_API_VERSION < 202006
# error "Please update your version of Symbiotic EDA flavored Verific."
#endif
@@ -1109,7 +1109,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
- import_attributes(wire->attributes, netbus, nl);
+ MapIter mibus;
+ FOREACH_NET_OF_NETBUS(netbus, mibus, net) {
+ if (net)
+ import_attributes(wire->attributes, net, nl);
+ break;
+ }
RTLIL::Const initval = Const(State::Sx, GetSize(wire));
bool initval_valid = false;
@@ -1882,7 +1887,7 @@ struct VerificExtNets
new_net = new Net(name.c_str());
nl->Add(new_net);
- Net *n YS_ATTRIBUTE(unused) = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
+ Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
log_assert(n == ca_net);
}
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 6195bb149..f2241066f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -528,6 +528,12 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
".*" { return TOK_WILDCARD_CONNECT; }
+"|=" { SV_KEYWORD(TOK_OR_ASSIGN); }
+"&=" { SV_KEYWORD(TOK_AND_ASSIGN); }
+"+=" { SV_KEYWORD(TOK_PLUS_ASSIGN); }
+"-=" { SV_KEYWORD(TOK_SUB_ASSIGN); }
+"^=" { SV_KEYWORD(TOK_XOR_ASSIGN); }
+
[-+]?[=*]> {
if (!specify_mode) REJECT;
yylval->string = new std::string(yytext);
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index bbf1a436b..0fdf2b516 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -256,7 +256,7 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_WILDCARD_CONNECT
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
-%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
+%token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_PLUS_ASSIGN TOK_ALWAYS TOK_INITIAL
%token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
%token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
%token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@@ -269,7 +269,8 @@ static void rewriteAsMemoryNode(AstNode *node, AstNode *rangeNode)
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
%token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
%token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
-%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
+%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_UNION
+%token TOK_OR_ASSIGN TOK_XOR_ASSIGN TOK_AND_ASSIGN TOK_SUB_ASSIGN
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@@ -436,7 +437,7 @@ module:
mod->str = *$4;
append_attr(mod, $1);
delete $4;
- } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
+ } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
if (port_stubs.size() != 0)
frontend_verilog_yyerror("Missing details for module port `%s'.",
port_stubs.begin()->first.c_str());
@@ -557,7 +558,7 @@ package:
current_ast_mod = mod;
mod->str = *$4;
append_attr(mod, $1);
- } ';' package_body TOK_ENDPACKAGE {
+ } ';' package_body TOK_ENDPACKAGE opt_label {
ast_stack.pop_back();
current_ast_mod = NULL;
exitTypeScope();
@@ -2335,6 +2336,46 @@ simple_behavioral_stmt:
ast_stack.back()->children.push_back(node);
SET_AST_NODE_LOC(node, @2, @5);
append_attr(node, $1);
+ } |
+ attr lvalue TOK_XOR_ASSIGN delay expr {
+ AstNode *xor_node = new AstNode(AST_BIT_XOR, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, xor_node);
+ SET_AST_NODE_LOC(xor_node, @2, @5);
+ SET_AST_NODE_LOC(node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_OR_ASSIGN delay expr {
+ AstNode *or_node = new AstNode(AST_BIT_OR, $2->clone(), $5);
+ SET_AST_NODE_LOC(or_node, @2, @5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, or_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_PLUS_ASSIGN delay expr {
+ AstNode *add_node = new AstNode(AST_ADD, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, add_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ SET_AST_NODE_LOC(add_node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_SUB_ASSIGN delay expr {
+ AstNode *sub_node = new AstNode(AST_SUB, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, sub_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ SET_AST_NODE_LOC(sub_node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
+ } |
+ attr lvalue TOK_AND_ASSIGN delay expr {
+ AstNode *and_node = new AstNode(AST_BIT_AND, $2->clone(), $5);
+ AstNode *node = new AstNode(AST_ASSIGN_EQ, $2, and_node);
+ SET_AST_NODE_LOC(node, @2, @5);
+ SET_AST_NODE_LOC(and_node, @2, @5);
+ ast_stack.back()->children.push_back(node);
+ append_attr(node, $1);
};
// this production creates the obligatory if-else shift/reduce conflict
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-13 05:35:30 +0000