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-rw-r--r--frontends/ast/genrtlil.cc1
-rw-r--r--frontends/ilang/ilang_parser.y3
2 files changed, 4 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d35335747..93fcfb396 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1058,6 +1058,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
wire->port_input = is_input;
wire->port_output = is_output;
wire->upto = range_swapped;
+ wire->is_signed = is_signed;
for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT)
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index 8e21fb176..43b628e09 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -192,6 +192,9 @@ wire_options:
wire_options TOK_UPTO {
current_wire->upto = true;
} |
+ wire_options TOK_SIGNED {
+ current_wire->is_signed = true;
+ } |
wire_options TOK_OFFSET TOK_INT {
current_wire->start_offset = $3;
} |