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diff --git a/btor.ys b/btor.ys
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+#design should be loaded before executing 
+
+#high level synthesis
+#################
+#converting processes to cells
+proc; 
+opt;
+#converting pmux to mux
+techmap -map techlibs/common/pmux2mux.v;
+opt;
+#converting asyn memory write to syn memory
+memory_dff; 
+opt;
+#flatten design
+flatten;
+opt;
+#adding temporary wires for cell ports
+scatter;
+#writing btor
+write_btor design.btor;