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-rw-r--r--backends/spice/spice.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 2c614178b..12e2c6695 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -120,7 +120,7 @@ struct SpiceBackend : public Backend {
log("Write the current design to an SPICE netlist file.\n");
log("\n");
log(" -big_endian\n");
- log(" generate multi-bit ports in MSB first order \n");
+ log(" generate multi-bit ports in MSB first order\n");
log(" (default is LSB first)\n");
log("\n");
log(" -neg net_name\n");