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-rw-r--r--backends/cxxrtl/cxxrtl_backend.cc90
1 files changed, 40 insertions, 50 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 94e823075..909e1325d 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -171,11 +171,6 @@ struct Scheduler {
}
};
-bool is_input_wire(const RTLIL::Wire *wire)
-{
- return wire->port_input && !wire->port_output;
-}
-
bool is_unary_cell(RTLIL::IdString type)
{
return type.in(
@@ -202,7 +197,7 @@ bool is_extending_cell(RTLIL::IdString type)
bool is_elidable_cell(RTLIL::IdString type)
{
return is_unary_cell(type) || is_binary_cell(type) || type.in(
- ID($mux), ID($concat), ID($slice));
+ ID($mux), ID($concat), ID($slice), ID($pmux));
}
bool is_sync_ff_cell(RTLIL::IdString type)
@@ -804,7 +799,7 @@ struct CxxrtlWorker {
default:
log_assert(false);
}
- } else if (unbuffered_wires[chunk.wire] || is_input_wire(chunk.wire)) {
+ } else if (unbuffered_wires[chunk.wire]) {
f << mangle(chunk.wire);
} else {
f << mangle(chunk.wire) << (is_lhs ? ".next" : ".curr");
@@ -947,6 +942,21 @@ struct CxxrtlWorker {
f << " : ";
dump_sigspec_rhs(cell->getPort(ID::A));
f << ")";
+ // Parallel (one-hot) muxes
+ } else if (cell->type == ID($pmux)) {
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int s_width = cell->getParam(ID::S_WIDTH).as_int();
+ for (int part = 0; part < s_width; part++) {
+ f << "(";
+ dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
+ f << " ? ";
+ dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
+ f << " : ";
+ }
+ dump_sigspec_rhs(cell->getPort(ID::A));
+ for (int part = 0; part < s_width; part++) {
+ f << ")";
+ }
// Concats
} else if (cell->type == ID($concat)) {
dump_sigspec_rhs(cell->getPort(ID::B));
@@ -1013,35 +1023,6 @@ struct CxxrtlWorker {
f << " = ";
dump_cell_elided(cell);
f << ";\n";
- // Parallel (one-hot) muxes
- } else if (cell->type == ID($pmux)) {
- int width = cell->getParam(ID::WIDTH).as_int();
- int s_width = cell->getParam(ID::S_WIDTH).as_int();
- bool first = true;
- for (int part = 0; part < s_width; part++) {
- f << (first ? indent : " else ");
- first = false;
- f << "if (";
- dump_sigspec_rhs(cell->getPort(ID::S).extract(part));
- f << ") {\n";
- inc_indent();
- f << indent;
- dump_sigspec_lhs(cell->getPort(ID::Y));
- f << " = ";
- dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width));
- f << ";\n";
- dec_indent();
- f << indent << "}";
- }
- f << " else {\n";
- inc_indent();
- f << indent;
- dump_sigspec_lhs(cell->getPort(ID::Y));
- f << " = ";
- dump_sigspec_rhs(cell->getPort(ID::A));
- f << ";\n";
- dec_indent();
- f << indent << "}\n";
// Flip-flops
} else if (is_ff_cell(cell->type)) {
if (cell->hasPort(ID::CLK) && cell->getPort(ID::CLK).is_wire()) {
@@ -1440,12 +1421,11 @@ struct CxxrtlWorker {
if (elided_wires.count(wire))
return;
- if (unbuffered_wires[wire]) {
- if (localized_wires[wire] == is_local_context) {
- dump_attrs(wire);
- f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
- }
- } else if (!is_local_context) {
+ if (localized_wires[wire] && is_local_context) {
+ dump_attrs(wire);
+ f << indent << "value<" << wire->width << "> " << mangle(wire) << ";\n";
+ }
+ if (!localized_wires[wire] && !is_local_context) {
std::string width;
if (wire->module->has_attribute(ID(cxxrtl_blackbox)) && wire->has_attribute(ID(cxxrtl_width))) {
width = wire->get_string_attribute(ID(cxxrtl_width));
@@ -1454,14 +1434,21 @@ struct CxxrtlWorker {
}
dump_attrs(wire);
- f << indent << (is_input_wire(wire) ? "value" : "wire") << "<" << width << "> " << mangle(wire);
+ f << indent;
+ if (wire->port_input && wire->port_output)
+ f << "/*inout*/ ";
+ else if (wire->port_input)
+ f << "/*input*/ ";
+ else if (wire->port_output)
+ f << "/*output*/ ";
+ f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire);
if (wire->has_attribute(ID::init)) {
f << " ";
dump_const_init(wire->attributes.at(ID::init));
}
f << ";\n";
if (edge_wires[wire]) {
- if (is_input_wire(wire)) {
+ if (unbuffered_wires[wire]) {
f << indent << "value<" << width << "> prev_" << mangle(wire);
if (wire->has_attribute(ID::init)) {
f << " ";
@@ -1472,7 +1459,7 @@ struct CxxrtlWorker {
for (auto edge_type : edge_types) {
if (edge_type.first.wire == wire) {
std::string prev, next;
- if (is_input_wire(wire)) {
+ if (unbuffered_wires[wire]) {
prev = "prev_" + mangle(edge_type.first.wire);
next = mangle(edge_type.first.wire);
} else {
@@ -1595,9 +1582,9 @@ struct CxxrtlWorker {
inc_indent();
f << indent << "bool changed = false;\n";
for (auto wire : module->wires()) {
- if (elided_wires.count(wire) || unbuffered_wires.count(wire))
+ if (elided_wires.count(wire))
continue;
- if (is_input_wire(wire)) {
+ if (unbuffered_wires[wire]) {
if (edge_wires[wire])
f << indent << "prev_" << mangle(wire) << " = " << mangle(wire) << ";\n";
continue;
@@ -1974,6 +1961,8 @@ struct CxxrtlWorker {
if (module->get_bool_attribute(ID(cxxrtl_blackbox))) {
for (auto port : module->ports) {
RTLIL::Wire *wire = module->wire(port);
+ if (wire->port_input && !wire->port_output)
+ unbuffered_wires.insert(wire);
if (wire->has_attribute(ID(cxxrtl_edge))) {
RTLIL::Const edge_attr = wire->attributes[ID(cxxrtl_edge)];
if (!(edge_attr.flags & RTLIL::CONST_FLAG_STRING) || (int)edge_attr.decode_string().size() != GetSize(wire))
@@ -2162,13 +2151,14 @@ struct CxxrtlWorker {
for (auto wire : module->wires()) {
if (feedback_wires[wire]) continue;
- if (wire->port_id != 0) continue;
- if (wire->get_bool_attribute(ID::keep)) continue;
+ if (wire->port_output && !module->get_bool_attribute(ID::top)) continue;
if (wire->name.begins_with("$") && !unbuffer_internal) continue;
if (wire->name.begins_with("\\") && !unbuffer_public) continue;
- if (edge_wires[wire]) continue;
if (flow.wire_sync_defs.count(wire) > 0) continue;
unbuffered_wires.insert(wire);
+ if (edge_wires[wire]) continue;
+ if (wire->get_bool_attribute(ID::keep)) continue;
+ if (wire->port_input || wire->port_output) continue;
if (wire->name.begins_with("$") && !localize_internal) continue;
if (wire->name.begins_with("\\") && !localize_public) continue;
localized_wires.insert(wire);
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-31 12:08:55 +0000