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-rw-r--r--backends/aiger/xaiger.cc24
1 files changed, 24 insertions, 0 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 65792421f..4bdd54772 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -481,6 +481,7 @@ struct XAigerWriter
}
}
+ // Connect $currQ as an input to the flop box
if (box_module->get_bool_attribute("\\abc9_flop")) {
IdString port_name = "\\$currQ";
Wire *w = box_module->wire(port_name);
@@ -786,6 +787,29 @@ struct XAigerWriter
}
}
+ // For flops only, create an extra input for $currQ
+ if (box_module->get_bool_attribute("\\abc9_flop")) {
+ log_assert(holes_cell);
+
+ Wire *w = box_module->wire("\\$currQ");
+ Wire *holes_wire;
+ RTLIL::SigSpec port_wire;
+ for (int i = 0; i < GetSize(w); i++) {
+ box_inputs++;
+ holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+ if (!holes_wire) {
+ holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+ holes_wire->port_input = true;
+ holes_wire->port_id = port_id++;
+ holes_module->ports.push_back(holes_wire->name);
+ }
+ port_wire.append(holes_wire);
+ }
+ w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()), GetSize(w));
+ w->set_bool_attribute("\\hierconn");
+ holes_module->connect(w, port_wire);
+ }
+
write_h_buffer(box_inputs);
write_h_buffer(box_outputs);
write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());