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Diffstat (limited to 'README')
| -rw-r--r-- | README | 93 |
1 files changed, 73 insertions, 20 deletions
@@ -3,7 +3,7 @@ | | | yosys -- Yosys Open SYnthesis Suite | | | - | Copyright (C) 2012 - 2015 Clifford Wolf <clifford@clifford.at> | + | Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | @@ -56,14 +56,14 @@ For example on Ubuntu Linux 14.04 LTS the following commands will install all prerequisites for building yosys: $ yosys_deps="build-essential clang bison flex libreadline-dev gawk - tcl-dev libffi-dev git mercurial graphviz xdot pkg-config" + tcl-dev libffi-dev git mercurial graphviz xdot pkg-config python3" $ sudo apt-get install $yosys_deps There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well as a source distribution for Visual Studio. Visit the Yosys download page for more information: - http://www.clifford.at/yosys/download.html + http://www.clifford.at/yosys/download.html To configure the build system to use a specific compiler, use one of @@ -84,7 +84,7 @@ To build Yosys simply type 'make' in this directory. $ sudo make install Note that this also downloads, builds and installs ABC (using yosys-abc -as executeable name). +as executable name). Yosys can be used with the interactive command shell, with synthesis scripts or with command line arguments. Let's perform @@ -98,7 +98,7 @@ commands and "help <command>" to print details on the specified command: yosys> help help -reading the design using the verilog frontend: +reading the design using the Verilog frontend: yosys> read_verilog tests/simple/fiedler-cooley.v @@ -127,7 +127,7 @@ translating netlist to gate logic and perform some simple optimizations: yosys> techmap; opt -write design netlist to a new verilog file: +write design netlist to a new Verilog file: yosys> write_verilog synth.v @@ -190,15 +190,13 @@ for the given cell library: clean If you do not have a liberty file but want to test this synthesis script, -you can use the file techlibs/cmos/cmos_cells.lib from the yosys sources. +you can use the file examples/cmos/cmos_cells.lib from the yosys sources. -Various more complex liberty files (for testing) can be found here: +Liberty file downloads for and information about free and open ASIC standard +cell libraries can be found here: - http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/.. - ../cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib - ../cadence/lib/ami035/signalstorm/osu035_stdcells.lib - ../cadence/lib/tsmc018/signalstorm/osu018_stdcells.lib - ../cadence/lib/ami05/signalstorm/osu05_stdcells.lib + http://www.vlsitechnology.org/html/libraries.html + http://www.vlsitechnology.org/synopsys/vsclib013.lib The command "synth" provides a good default synthesis script (see "help synth"). If possible a synthesis script should borrow from "synth". For example: @@ -223,7 +221,7 @@ The following Verilog-2005 features are not supported by yosys and there are currently no plans to add support for them: -- Non-sythesizable language features as defined in +- Non-synthesizable language features as defined in IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 - The "tri", "triand", "trior", "wand" and "wor" net types @@ -257,6 +255,11 @@ Verilog Attributes and non-standard features - The "mem2reg" attribute on modules or arrays forces the early conversion of arrays to separate registers. +- The "nomeminit" attribute on modules or arrays prohibits the + creation of initialized memories. This effectively puts "mem2reg" + on all memories that are written to in an "initial" block and + are not ROMs. + - The "nolatches" attribute on modules or always-blocks prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. This does @@ -266,7 +269,7 @@ Verilog Attributes and non-standard features storage element. The register itself will always have all bits set to 'x' (undefined). The variable may only be used as blocking assigned temporary variable within an always block. This is mostly used internally - by yosys to synthesize verilog functions and access arrays. + by yosys to synthesize Verilog functions and access arrays. - The "onehot" attribute on wires mark them as onehot state register. This is used for example for memory port sharing and set by the fsm_map pass. @@ -274,7 +277,7 @@ Verilog Attributes and non-standard features - The "blackbox" attribute on modules is used to mark empty stub modules that have the same ports as the real thing but do not contain information on the internal configuration. This modules are only used by the synthesis - passes to identify input and output ports of cells. The verilog backend + passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. - The "keep" attribute on cells and wires is used to mark objects that should @@ -283,6 +286,9 @@ Verilog Attributes and non-standard features Setting the "keep" attribute on a module has the same effect as setting it on all instances of the module. +- The "keep_hierarchy" attribute on cells and modules keeps the "flatten" + command from flattening the indicated cells and modules. + - The "init" attribute on wires is set by the frontend when a register is initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis to add the necessary reset logic. @@ -292,26 +298,35 @@ Verilog Attributes and non-standard features with "-top". Other commands, such as "flatten" and various backends use this attribute to determine the top module. +- The "src" attribute is set on cells and wires created by to the string + "<hdl-file-name>:<line-number>" by the HDL front-end and is then carried + through the synthesis. When entities are combined, a new |-separated + string is created that contains all the string from the original entities. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset by adding an empty {* *} statement.) +- In module parameter and port declarations, and cell port and parameter + lists, a trailing comma is ignored. This simplifies writing verilog code + generators a bit in some cases. + - Modules can be declared with "module mod_name(...);" (with three dots instead of a list of module ports). With this syntax it is sufficient to simply declare a module port as 'input' or 'output' in the module body. -- When defining a macro with `define, all text between tripple double quotes +- When defining a macro with `define, all text between triple double quotes is interpreted as macro body, even if it contains unescaped newlines. The - tripple double quotes are removed from the macro body. For example: + tipple double quotes are removed from the macro body. For example: `define MY_MACRO(a, b) """ assign a = 23; assign b = 42; """ -- The attribute "via_celltype" can be used to implement a verilog task or +- The attribute "via_celltype" can be used to implement a Verilog task or function by instantiating the specified cell type. The value is the name of the cell type to use. For functions the name of the output port can be specified by appending it to the cell type separated by a whitespace. @@ -351,9 +366,13 @@ Verilog Attributes and non-standard features $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax <size>'s?[bodh]<value>) support constant - expressions as <size>. If the expresion is not a simple identifier, it + expressions as <size>. If the expression is not a simple identifier, it must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010 +- The system tasks $finish and $display are supported in initial blocks + in and unconditional context (only if/case statements on parameters + and constant values). The intended use for this is synthesis-time DRC. + Supported features from SystemVerilog ===================================== @@ -368,3 +387,37 @@ from SystemVerilog: - The keywords "always_comb", "always_ff" and "always_latch", "logic" and "bit" are supported. + +Building the documentation +========================== + +Note that there is no need to build the manual if you just want to read it. +Simply download the PDF from http://www.clifford.at/yosys/documentation.html +instead. + +On Ubuntu, texlive needs these packages to be able to build the manual: + + sudo apt-get install texlive-binaries + sudo apt-get install texlive-science # install algorithm2e.sty + sudo apt-get install texlive-bibtex-extra # gets multibib.sty + sudo apt-get install texlive-fonts-extra # gets skull.sty and dsfont.sty + sudo apt-get install texlive-publishers # IEEEtran.cls + +Also the non-free font luximono should be installed, there is unfortulately +no Ubuntu package for this so it should be installed separately using +`getnonfreefonts`: + + wget https://tug.org/fonts/getnonfreefonts/install-getnonfreefonts + sudo texlua install-getnonfreefonts # will install to /usr/local by default, can be changed by editing BINDIR at MANDIR at the top of the script + getnonfreefonts luximono # installs to /home/user/texmf + +Then execute, from the root of the repository: + + make manual + +Notes: + +- To run `make manual` you need to have installed yosys with `make install`, + otherwise it will fail on finding `kernel/yosys.h` while building + `PRESENTATION_Prog`. + |