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Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 11 |
1 files changed, 6 insertions, 5 deletions
@@ -259,11 +259,7 @@ for them: - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types -- The ``config`` keyword and library map files - -- The ``disable``, ``primitive`` and ``specify`` statements - -- Latched logic (is synthesized as logic with feedback loops) +- The ``config`` and ``disable`` keywords and library map files Verilog Attributes and non-standard features @@ -424,6 +420,11 @@ Verilog Attributes and non-standard features in an unconditional context (only if/case statements on parameters and constant values). The intended use for this is synthesis-time DRC. +- There is limited support for converting specify .. endspecify statements to + special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in + blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this + functionality. (By default specify .. endspecify blocks are ignored.) + Non-standard or SystemVerilog features for formal verification ============================================================== |