diff options
Diffstat (limited to 'CodingReadme')
| -rw-r--r-- | CodingReadme | 116 |
1 files changed, 71 insertions, 45 deletions
diff --git a/CodingReadme b/CodingReadme index 46624e9c7..cbe1fb8be 100644 --- a/CodingReadme +++ b/CodingReadme @@ -93,6 +93,9 @@ creates a bijective map from K to the integers. For example: It is not possible to remove elements from an idict. +Finally mfp<K> implements a merge-find set data structure (aka. disjoint-set or +union-find) over the type K ("mfp" = merge-find-promote). + 2. Standard STL data types In Yosys we use std::vector<T> and std::string whenever applicable. When @@ -154,6 +157,41 @@ only use one wire from such a group of connected wires. For example: log("%d\n", sigmap(a) == sigmap(b)); // will print 1 +Using the RTLIL Netlist Format +------------------------------ + +In the RTLIL netlist format the cell ports contain SigSpecs that point to the +Wires. There are no references in the other direction. This has two direct +consequences: + +(1) It is very easy to go from cells to wires but hard to go in the other way. + +(2) There is no danger in removing cells from the netlists, but removing wires +can break the netlist format when there are still references to the wire +somewhere in the netlist. + +The solution to (1) is easy: Create custom indexes that allow you to make fast +lookups for the wire-to-cell direction. You can either use existing generic +index structures to do that (such as the ModIndex class) or write your own +index. For many application it is simplest to construct a custom index. For +example: + + SigMap sigmap(module); + dict<SigBit, Cell*> sigbit_to_driver_index; + + for (auto cell : module->cells()) + for (auto &conn : cell->connections()) + if (cell->output(conn.first)) + for (auto bit : sigmap(conn.second)) + sigbit_to_driver_index[bit] = cell; + +Regarding (2): There is a general theme in Yosys that you don't remove wires +from the design. You can rename them, unconnect them, but you do not actually remove +the Wire object from the module. Instead you let the "clean" command take care +of the dangling wires. On the other hand it is safe to remove cells (as long as +you make sure this does not invalidate a custom index you are using in your code). + + Example Code ------------ @@ -193,15 +231,15 @@ Formatting of code on its own line for larger blocks, especially blocks that contains blank lines. -- Otherwise stick to the Linux Kernel Coding Stlye: +- Otherwise stick to the Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/CodingStyle -C++ Langugage +C++ Language ------------- Yosys is written in C++11. At the moment only constructs supported by -gcc 4.6 are allowed in Yosys code. This will change in future releases. +gcc 4.8 are allowed in Yosys code. This will change in future releases. In general Yosys uses "int" instead of "size_t". To avoid compiler warnings for implicit type casts, always use "GetSize(foobar)" instead @@ -227,7 +265,7 @@ Creating the Visual Studio Template Project [ ] Add to source control [X] Console applications - [X] Empty Projcect + [X] Empty Project [ ] SDL checks 2. Open YosysVS Project Properties @@ -268,7 +306,7 @@ Things to do after finalizing the cell interface: - Add support to kernel/satgen.h for the new cell type - Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom) - - Maybe add support to the verilog backend for dumping such cells as expression + - Maybe add support to the Verilog backend for dumping such cells as expression @@ -282,22 +320,18 @@ Update the CHANGELOG file: vi CHANGELOG -Run all tests with "make config-{clang,gcc,gcc-4.6}": +Update and check documentation: cd ~yosys - make clean - make test - make vloghtb - make install - - cd ~yosys-bigsim - make clean - make full + make update-manual + make manual + - sanity check the figures in the appnotes and presentation + - if there are any odd things -> investigate + - make cosmetic changes to the .tex files if necessary - cd ~vloghammer - make purge gen_issues gen_samples - make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world - chromium-browser report.html + cd ~yosys + vi README CodingReadme + - is the information provided in those file still up to date Then with default config setting: @@ -311,28 +345,20 @@ Then with default config setting: ./yosys -p 'synth; show' tests/simple/fiedler-cooley.v ./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v - cd ~yosys - make manual - - sanity check the figures in the appnotes and presentation - - if there are any odd things -> investigate - - make cosmetic changes to the .tex files if necessary - - -Also with default config setting: - - cd ~yosys/techlibs/cmos + cd ~yosys/examples/cmos bash testbench.sh - cd ~yosys/techlibs/xilinx/example_basys3 + cd ~yosys/examples/basys3 bash run.sh Test building plugins with various of the standard passes: yosys-config --build test.so equiv_simple.cc + - also check the code examples in CodingReadme -Finally if a current verific library is available: +And if a version of the verific library is currently available: cd ~yosys cat frontends/verific/build_amd64.txt @@ -342,12 +368,22 @@ Finally if a current verific library is available: ../../yosys test_navre.ys -Release candiate: +Finally run all tests with "make config-{clang,gcc,gcc-4.8}": - - create branch yosys-x.y.z-rc and push to github - - contact the usual suspects per mail and ask them to test - - post on the reddit and ask people to test - - commit KISS fixes to the -rc branch if necessary + cd ~yosys + make clean + make test + make vloghtb + make install + + cd ~yosys-bigsim + make clean + make full + + cd ~vloghammer + make purge gen_issues gen_samples + make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world + chromium-browser report.html Release: @@ -359,7 +395,6 @@ Release: - push tag to github - post changelog on github - post short release note on reddit - - delete -rc branch from github Updating the website: @@ -376,12 +411,3 @@ Updating the website: git commit -am update make push - -In master branch: - - git merge {release-tag} - - set version to x.y.z+ in Makefile - - add section "Yosys x.y.z .. x.y.z+" to CHANGELOG - git commit --amend -am "Yosys x.y.z+" - - |