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Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 165 |
1 files changed, 164 insertions, 1 deletions
@@ -2,9 +2,172 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.11 .. Yosys 0.11-dev +Yosys 0.19 .. Yosys 0.19-dev -------------------------- +Yosys 0.18 .. Yosys 0.19 +-------------------------- + * New commands and options + - Added option "-rom-only" to "memory_libmap" pass + - Added option "-smtcheck" to "hierarchy" pass + - Added option "-keepdc" to "memory_libmap" pass + - Added option "-suffix" to "rename" pass + - Added "gatemate_foldinv" pass + + * Formal Verification + - Added support for $pos cell in btor backend + - Added the "smtlib2_module" and "smtlib2_comb_expr" attributes + + * GateMate support + - Added LUT tree mapping + + * Verific support + - Added option "-pp" to "verific -import" + +Yosys 0.17 .. Yosys 0.18 +-------------------------- + * Various + - Migrated most flows to use memory_libmap based memory inference + + * New commands and options + - Added "memory_libmap" pass + - Added "memory_bmux2rom" pass - converts muxes to ROMs + - Added "memory_dff -no-rw-check" + - Added "opt_ffinv" pass - push inverters through FFs + - Added "proc_rom" pass - convert switches to ROMs + - Added "proc -norom" option - will omit the proc_rom pass + - Added option "-no-rw-check" to synth passes + - Added "synth_ice40 -spram" option for automatic inference of SB_SPRAM256KA + - Added options "-nobram" and "-nolutram" to synth_machxo2 pass + + * Formal Verification + - Fixed the signedness of $past's return value to be the same as the + argument's instead of always unsigned. + + * Verilog + - Fixed an issue where simplifying case statements by removing unreachable + cases could result in the wrong signedness being used for comparison with + the remaining cases + - Fixed size and signedness computation for expressions containing array + querying functions + - Fixed size and signedness computation of functions used in ternary + expressions or case item expressions + + * Verific support + - Proper file location for readmem commands + - Added "-vlog-libext" option to specify search extension for libraries + +Yosys 0.16 .. Yosys 0.17 +-------------------------- + * New commands and options + - Added "write_jny" ( JSON netlist metadata format ) + - Added "tribuf -formal" + + * SystemVerilog + - Fixed automatic `nosync` inference for local variables in `always_comb` + procedures not applying to nested blocks and blocks in functions + +Yosys 0.15 .. Yosys 0.16 +-------------------------- + * Various + - Added BTOR2 witness file co-simulation. + - Simulation calls external vcd2fst for VCD conversion. + - Added fst2tb pass - generates testbench for the circuit using + the given top-level module and simulus signal from FST file. + - yosys-smtbmc: Option to keep going after failed assertions in BMC mode + + * Verific support + - Import modules in alphabetic (reproducable) order. + +Yosys 0.14 .. Yosys 0.15 +-------------------------- + + * Various + - clk2fflogic: nice names for autogenerated signals + - simulation include support for all flip-flop types. + - Added AIGER witness file co-simulation. + + * Verilog + - Fixed evaluation of constant functions with variables or arguments with + reversed dimensions + - Fixed elaboration of dynamic range assignments where the vector is + reversed or is not zero-indexed + - Added frontend support for time scale delay values (e.g., `#1ns`) + + * SystemVerilog + - Added support for accessing whole sub-structures in expressions + + * New commands and options + - Added glift command, used to create gate-level information flow tracking + (GLIFT) models by the "constructive mapping" approach + + * Verific support + - Ability to override default parser mode for verific -f command. + +Yosys 0.13 .. Yosys 0.14 +-------------------------- + + * Various + - Added $bmux and $demux cells and related optimization patterns. + + * New commands and options + - Added "bmuxmap" and "dmuxmap" passes + - Added "-fst" option to "sim" pass for writing FST files + - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate", + "-sim-gold" options to "sim" pass for co-simulation + + * Anlogic support + - Added support for BRAMs + +Yosys 0.12 .. Yosys 0.13 +-------------------------- + + * Various + - Use "read" command to parse HDL files from Yosys command-line + - Added "yosys -r <topmodule>" command line option + - write_verilog: dump zero width sigspecs correctly + + * SystemVerilog + - Fixed regression preventing the use array querying functions in case + expressions and case item expressions + - Fixed static size casts inadvertently limiting the result width of binary + operations + - Fixed static size casts ignoring expression signedness + - Fixed static size casts not extending unbased unsized literals + - Added automatic `nosync` inference for local variables in `always_comb` + procedures which are always assigned before they are used to avoid errant + latch inference + + * New commands and options + - Added "clean_zerowidth" pass + + * Verific support + - Add YOSYS to the implicitly defined verilog macros in verific + +Yosys 0.11 .. Yosys 0.12 +-------------------------- + + * Various + - Added iopadmap native support for negative-polarity output enable + - ABC update + + * SystemVerilog + - Support parameters using struct as a wiretype + + * New commands and options + - Added "-genlib" option to "abc" pass + - Added "sta" very crude static timing analysis pass + + * Verific support + - Fixed memory block size in import + + * New back-ends + - Added support for GateMate FPGA from Cologne Chip AG + + * Intel ALM support + - Added preliminary Arria V support + + Yosys 0.10 .. Yosys 0.11 -------------------------- |