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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 14:21:00 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-21 14:21:00 -0700 |
| commit | fb09c6219b057100d2e43028ec710888c20924fd (patch) | |
| tree | 7f1de06040bf3276fb414acf68a12eac1421389d /passes/opt/opt_expr.cc | |
| parent | 283e33ba5aad3a66bd14c30e1f52361c5f4c9789 (diff) | |
| parent | c907899422884d959632ed42c6589a0720b681e4 (diff) | |
| download | yosys-fb09c6219b057100d2e43028ec710888c20924fd.tar.gz yosys-fb09c6219b057100d2e43028ec710888c20924fd.tar.bz2 yosys-fb09c6219b057100d2e43028ec710888c20924fd.zip | |
Merge remote-tracking branch 'origin/master' into xc7mux
Diffstat (limited to 'passes/opt/opt_expr.cc')
| -rw-r--r-- | passes/opt/opt_expr.cc | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index b445afdc8..512ef0cbf 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -61,7 +61,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } if (wire->port_input) driven_signals.add(sigmap(wire)); - if (wire->port_output) + if (wire->port_output || wire->get_bool_attribute("\\keep")) used_signals.add(sigmap(wire)); all_signals.add(sigmap(wire)); } @@ -88,7 +88,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) } } - log_debug("Setting undriven signal in %s to constant: %s = %s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(val)); + log_debug("Setting undriven signal in %s to constant: %s = %s\n", log_id(module), log_signal(sig), log_signal(val)); module->connect(sig, val); did_something = true; } @@ -104,10 +104,15 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) if (SigBit(initval[i]) == sig[i]) initval[i] = State::Sx; } - if (initval.is_fully_undef()) + if (initval.is_fully_undef()) { + log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire)); wire->attributes.erase("\\init"); - else + did_something = true; + } else if (initval != wire->attributes.at("\\init")) { + log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval)); wire->attributes["\\init"] = initval; + did_something = true; + } } } } |