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| author | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
|---|---|---|
| committer | Diego H <diego@symbioticeda.com> | 2019-12-12 13:40:05 -0600 |
| commit | ab6ac8327f28b2ba9530c81cdbb5091a1ef91032 (patch) | |
| tree | 9e2716d6d621eeeda85896b7b2993de517bb931a /passes/memory | |
| parent | 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b (diff) | |
| parent | 2666482282421bb54213ba01054111eadc401373 (diff) | |
| download | yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.gz yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.tar.bz2 yosys-ab6ac8327f28b2ba9530c81cdbb5091a1ef91032.zip | |
Merge https://github.com/YosysHQ/yosys into bram_xilinx
Diffstat (limited to 'passes/memory')
| -rw-r--r-- | passes/memory/memory_collect.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6acbce62f..9dcb3f024 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->setPort("\\RD_DATA", sig_rd_data); mem->setPort("\\RD_EN", sig_rd_en); + // Copy attributes from RTLIL memory to $mem + for (auto attr : memory->attributes) + mem->attributes[attr.first] = attr.second; + for (auto c : memcells) module->remove(c); |