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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-16 10:03:07 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-16 10:03:07 +0200 |
| commit | 964a67ac4194bb85fb3cb7a90a62dc1e4a685ea4 (patch) | |
| tree | 3b12cea2429965e5cd065780d4cb92da856ac056 /frontends/vhdl2verilog/Makefile.inc | |
| parent | 0f9ca49dc6047ad5634782de23040ec57601debd (diff) | |
| download | yosys-964a67ac4194bb85fb3cb7a90a62dc1e4a685ea4.tar.gz yosys-964a67ac4194bb85fb3cb7a90a62dc1e4a685ea4.tar.bz2 yosys-964a67ac4194bb85fb3cb7a90a62dc1e4a685ea4.zip | |
Added note to "make test": use git checkout of iverilog
Diffstat (limited to 'frontends/vhdl2verilog/Makefile.inc')
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