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author | Jannis Harder <me@jix.one> | 2023-03-20 12:50:14 +0100 |
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committer | Jannis Harder <me@jix.one> | 2023-03-20 12:52:46 +0100 |
commit | fb1c2be76ba065a3da04f279b11e1ed2e59c75c5 (patch) | |
tree | f452376b633c339d43d7e2e16cc991465ebeef25 /frontends/verilog/verilog_lexer.l | |
parent | 61da330a38812a0a394131f9f434c736cb2239cf (diff) | |
download | yosys-fb1c2be76ba065a3da04f279b11e1ed2e59c75c5.tar.gz yosys-fb1c2be76ba065a3da04f279b11e1ed2e59c75c5.tar.bz2 yosys-fb1c2be76ba065a3da04f279b11e1ed2e59c75c5.zip |
verilog: Support void functions
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
Diffstat (limited to 'frontends/verilog/verilog_lexer.l')
-rw-r--r-- | frontends/verilog/verilog_lexer.l | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 958809319..249986668 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -276,6 +276,7 @@ TIME_SCALE_SUFFIX [munpf]?s "byte" { SV_KEYWORD(TOK_BYTE); } "shortint" { SV_KEYWORD(TOK_SHORTINT); } "longint" { SV_KEYWORD(TOK_LONGINT); } +"void" { SV_KEYWORD(TOK_VOID); } "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } "s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } |