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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 16:33:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 16:33:40 -0700 |
| commit | e529872b0170ba269db2d00c96108c86b260e864 (patch) | |
| tree | f11a17dbd61b5f5519c7b693c800870e58556bcf /backends/aiger/xaiger.cc | |
| parent | 5e9ae90cbba4e9c2abfe5d6a1b90c2256aae1615 (diff) | |
| download | yosys-e529872b0170ba269db2d00c96108c86b260e864.tar.gz yosys-e529872b0170ba269db2d00c96108c86b260e864.tar.bz2 yosys-e529872b0170ba269db2d00c96108c86b260e864.zip | |
Remove need for $currQ port connection
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 52273e9b9..65792421f 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -483,12 +483,12 @@ struct XAigerWriter if (box_module->get_bool_attribute("\\abc9_flop")) { IdString port_name = "\\$currQ"; - RTLIL::Wire* w = box_module->wire(port_name); - SigSpec rhs = cell->getPort(port_name); + Wire *w = box_module->wire(port_name); + SigSpec rhs = module->wire(stringf("%s.$currQ", cell->name.c_str())); log_assert(GetSize(w) == GetSize(rhs)); int offset = 0; - for (auto b : rhs.bits()) { + for (auto b : rhs) { SigBit I = sigmap(b); if (b == RTLIL::Sx) b = State::S0; |