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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-23 08:35:53 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-23 08:35:53 -0800 |
| commit | 6eadd4390a3c9650912bac9fbf8bd309f0088217 (patch) | |
| tree | 7cf8909c23d51f1d566fb17c3f03137a38808450 /backends/aiger/xaiger.cc | |
| parent | d3fc94405f14a96a91463f618908c5a51a491507 (diff) | |
| download | yosys-6eadd4390a3c9650912bac9fbf8bd309f0088217.tar.gz yosys-6eadd4390a3c9650912bac9fbf8bd309f0088217.tar.bz2 yosys-6eadd4390a3c9650912bac9fbf8bd309f0088217.zip | |
write_xaiger to opt instead of just clean whiteboxes
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index af52daa0c..78496b13c 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -876,7 +876,7 @@ struct XAigerWriter RTLIL::Design *holes_design = new RTLIL::Design; module->design->modules_.erase(holes_module->name); holes_design->add(holes_module); - Pass::call(holes_design, "clean -purge"); + Pass::call(holes_design, "opt -purge"); std::stringstream a_buffer; XAigerWriter writer(holes_module, true /* holes_mode */); |