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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 15:35:33 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-30 15:35:33 -0800 |
| commit | 07355729341e5104cf83210af280cb0cc6e8c7de (patch) | |
| tree | 95a45d22175e8d35b599f9eae40372aa704bd3e0 /backends/aiger/xaiger.cc | |
| parent | fc4b8b89912c14f42b04a7c9f2ce350db3ce7c0b (diff) | |
| download | yosys-07355729341e5104cf83210af280cb0cc6e8c7de.tar.gz yosys-07355729341e5104cf83210af280cb0cc6e8c7de.tar.bz2 yosys-07355729341e5104cf83210af280cb0cc6e8c7de.zip | |
write_xaiger to use scratchpad for stats; cleanup abc9
Diffstat (limited to 'backends/aiger/xaiger.cc')
| -rw-r--r-- | backends/aiger/xaiger.cc | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index ce7b479ff..e7d767721 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -93,7 +93,6 @@ struct XAigerWriter dict<SigBit, int> ordered_outputs; vector<Cell*> box_list; - bool omode = false; int mkgate(int a0, int a1) { @@ -579,11 +578,6 @@ struct XAigerWriter aig_outputs.push_back(bit2aig(bit)); } - if (output_bits.empty()) { - output_bits.insert(State::S0); - omode = true; - } - for (auto bit : output_bits) { ordered_outputs[bit] = aig_o++; aig_outputs.push_back(bit2aig(bit)); @@ -594,12 +588,6 @@ struct XAigerWriter aig_o++; aig_outputs.push_back(ff_aig_map.at(bit)); } - - if (output_bits.empty()) { - aig_o++; - aig_outputs.push_back(0); - omode = true; - } } void write_aiger(std::ostream &f, bool ascii_mode) @@ -661,7 +649,6 @@ struct XAigerWriter f << "c"; - log_assert(!output_bits.empty()); auto write_buffer = [](std::stringstream &buffer, int i32) { int32_t i32_be = to_big_endian(i32); buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be)); @@ -922,6 +909,11 @@ struct XAigerWriter //f.write(buffer_str.data(), buffer_str.size()); f << stringf("Generated by %s\n", yosys_version_str); + + module->design->scratchpad_set_int("write_xaiger.num_ands", and_map.size()); + module->design->scratchpad_set_int("write_xaiger.num_wires", aig_map.size()); + module->design->scratchpad_set_int("write_xaiger.num_inputs", input_bits.size()); + module->design->scratchpad_set_int("write_xaiger.num_outputs", output_bits.size()); } void write_map(std::ostream &f, bool verbose_map) @@ -973,13 +965,9 @@ struct XAigerWriter f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name)); output_lines.sort(); - if (omode) - output_lines[State::S0] = "output 0 0 $__dummy__\n"; for (auto &it : output_lines) f << it.second; log_assert(output_lines.size() == output_bits.size()); - if (omode && output_bits.empty()) - f << "output " << output_lines.size() << " 0 $__dummy__\n"; wire_lines.sort(); for (auto &it : wire_lines) |