-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
-- use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
-- use PoC.physical.all;
package sim_types is
-- Simulation Task and Status Management
-- ===========================================================================
subtype T_SIM_PROCESS_ID is NATURAL range 0 to 1023;
subtype T_SIM_PROCESS_NAME is STRING(1 to 64);
subtype T_SIM_PROCESS_INSTNAME is STRING(1 to 256);
type T_SIM_PROCESS_STATUS is (
SIM_PROCESS_STATUS_ACTIVE,
SIM_PROCESS_STATUS_ENDED
);
type T_SIM_PROCESS is record
ID : T_SIM_PROCESS_ID;
Name : T_SIM_PROCESS_NAME;
InstanceName : T_SIM_PROCESS_INSTNAME;
Status : T_SIM_PROCESS_STATUS;
end record;
type T_SIM_PROCESS_VECTOR is array(NATURAL range <>) of T_SIM_PROCESS;
subtype T_SIM_TEST_ID is NATURAL range 0 to 1023;
subtype T_SIM_TEST_NAME is STRING(1 to 256);
type T_SIM_TEST_STATUS is (
SIM_TEST_STATUS_ACTIVE,
SIM_TEST_STATUS_ENDED
);
type T_SIM_TEST is record
ID : T_SIM_TEST_ID;
Name : T_SIM_TEST_NAME;
Status : T_SIM_TEST_STATUS;
end record;
type T_SIM_TEST_VECTOR is array(NATURAL range <>) of T_SIM_TEST;
-- clock generation
-- ===========================================================================
-- type T_PERCENT is INTEGER'range units
type T_PERCENT is range INTEGER'low to INTEGER'high units
ppb;
ppm = 1000 ppb;
permil = 1000 ppm;
percent = 10 permil;
one = 100 percent;
end units;
subtype T_WANDER is T_PERCENT range -1 one to 1 one;
subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one;
type T_DEGREE is range INTEGER'low to INTEGER'high units
second;
minute = 60 second;
deg = 60 minute;
end units;
subtype T_PHASE is T_DEGREE range -360 deg to 360 deg;
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE;
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
end package;
package body sim_types is
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
end package body;
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/*
* nextpnr -- Next Generation Place and Route
*
* Copyright (C) 2021 Symbiflow Authors
*
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "site_routing_cache.h"
#include "context.h"
#include "site_arch.impl.h"
NEXTPNR_NAMESPACE_BEGIN
void SiteRoutingSolution::store_solution(const SiteArch *ctx, const RouteNodeStorage *node_storage,
const SiteWire &driver, std::vector<size_t> solutions)
{
clear();
solution_sinks.reserve(solutions.size());
inverted.reserve(solutions.size());
can_invert.reserve(solutions.size());
for (size_t route : solutions) {
bool sol_inverted = false;
bool sol_can_invert = false;
SiteWire wire = node_storage->get_node(route)->wire;
solution_sinks.push_back(wire);
solution_offsets.push_back(solution_storage.size());
Node cursor = node_storage->get_node(route);
while (cursor.has_parent()) {
if (ctx->isInverting(cursor->pip) && !sol_can_invert) {
sol_inverted = !sol_inverted;
}
if (ctx->canInvert(cursor->pip)) {
sol_inverted = false;
sol_can_invert = true;
}
solution_storage.push_back(cursor->pip);
Node parent = cursor.parent();
NPNR_ASSERT(ctx->getPipDstWire(cursor->pip) == cursor->wire);
NPNR_ASSERT(ctx->getPipSrcWire(cursor->pip) == parent->wire);
cursor = parent;
}
inverted.push_back(sol_inverted);
can_invert.push_back(sol_can_invert);
NPNR_ASSERT(cursor->wire == driver);
}
solution_offsets.push_back(solution_storage.size());
}
bool SiteRoutingSolution::verify(const SiteArch *ctx, const SiteNetInfo &net)
{
pool<SiteWire> seen_users;
for (size_t i = 0; i < num_solutions(); ++i) {
SiteWire cursor = solution_sink(i);
NPNR_ASSERT(net.users.count(cursor) == 1);
seen_users.emplace(cursor);
auto begin = solution_begin(i);
auto end = solution_end(i);
for (auto iter = begin; iter != end; ++iter) {
SitePip pip = *iter;
NPNR_ASSERT(ctx->getPipDstWire(pip) == cursor);
cursor = ctx->getPipSrcWire(pip);
}
NPNR_ASSERT(net.driver == cursor);
}
return seen_users.size() == net.users.size();
}
SiteRoutingKey SiteRoutingKey::make(const SiteArch *ctx, const SiteNetInfo &site_net)
{
SiteRoutingKey out;
out.tile_type = ctx->site_info->tile_type;
out.site = ctx->site_info->site;
out.net_type = ctx->ctx->get_net_type(site_net.net);
out.driver_type = site_net.driver.type;
if (site_net.driver.type == SiteWire::SITE_WIRE) {
out.driver_index = site_net.driver.wire.index;
} else {
NPNR_ASSERT(site_net.driver.type == SiteWire::OUT_OF_SITE_SOURCE);
out.driver_index = -1;
}
out.user_types.reserve(site_net.users.size());
out.user_indicies.reserve(site_net.users.size());
std::vector<SiteWire> users;
users.reserve(site_net.users.size());
users.insert(users.begin(), site_net.users.begin(), site_net.users.end());
std::sort(users.begin(), users.end());
for (const SiteWire &user : users) {
out.user_types.push_back(user.type);
if (user.type == SiteWire::SITE_WIRE) {
out.user_indicies.push_back(user.wire.index);
} else {
NPNR_ASSERT(user.type == SiteWire::OUT_OF_SITE_SINK);
out.user_indicies.push_back(-1);
}
}
return out;
}
bool SiteRoutingCache::get_solution(const SiteArch *ctx, const SiteNetInfo &net, SiteRoutingSolution *solution) const
{
SiteRoutingKey key = SiteRoutingKey::make(ctx, net);
auto iter = cache_.find(key);
if (iter == cache_.end()) {
return false;
}
*solution = iter->second;
const auto &tile_type_data = ctx->site_info->chip_info().tile_types[ctx->site_info->tile_type];
for (SiteWire &wire : solution->solution_sinks) {
switch (wire.type) {
case SiteWire::SITE_WIRE:
wire.wire.tile = ctx->site_info->tile;
break;
case SiteWire::OUT_OF_SITE_SOURCE:
wire.net = net.net;
break;
case SiteWire::OUT_OF_SITE_SINK:
wire.net = net.net;
break;
case SiteWire::SITE_PORT_SINK: {
const auto &pip_data = tile_type_data.pip_data[wire.pip.index];
wire.pip.tile = ctx->site_info->tile;
wire.wire = canonical_wire(&ctx->site_info->chip_info(), ctx->site_info->tile, pip_data.dst_index);
break;
}
case SiteWire::SITE_PORT_SOURCE: {
const auto &pip_data = tile_type_data.pip_data[wire.pip.index];
wire.pip.tile = ctx->site_info->tile;
wire.wire = canonical_wire(&ctx->site_info->chip_info(), ctx->site_info->tile, pip_data.src_index);
break;
}
default:
NPNR_ASSERT(false);
}
}
for (SitePip &pip : solution->solution_storage) {
pip.pip.tile = ctx->site_info->tile;
switch (pip.type) {
case SitePip::SITE_PIP:
// Done!
break;
case SitePip::SITE_PORT:
// Done!
break;
case SitePip::SOURCE_TO_SITE_PORT:
NPNR_ASSERT(pip.wire.type == SiteWire::OUT_OF_SITE_SOURCE);
pip.wire.net = net.net;
break;
case SitePip::SITE_PORT_TO_SINK:
NPNR_ASSERT(pip.wire.type == SiteWire::OUT_OF_SITE_SINK);
pip.wire.net = net.net;
break;
case SitePip::SITE_PORT_TO_SITE_PORT:
pip.other_pip.tile = ctx->site_info->tile;
break;
default:
NPNR_ASSERT(false);
}
}
return solution->verify(ctx, net);
}
void SiteRoutingCache::add_solutions(const SiteArch *ctx, const SiteNetInfo &net, const SiteRoutingSolution &solution)
{
SiteRoutingKey key = SiteRoutingKey::make(ctx, net);
cache_[key] = solution;
}
void SiteRoutingCache::clear() { cache_.clear(); }
NEXTPNR_NAMESPACE_END
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