-- Synthesis context. -- Copyright (C) 2017 Tristan Gingold -- -- This file is part of GHDL. -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . with Ada.Unchecked_Conversion; with Tables; with Types_Utils; use Types_Utils; with Netlists.Folds; use Netlists.Folds; with Synth.Vhdl_Expr; use Synth.Vhdl_Expr; with Netlists.Locations; package body Synth.Vhdl_Context is package Extra_Tables is new Tables (Table_Component_Type => Extra_Vhdl_Instance_Type, Table_Index_Type => Instance_Id_Type, Table_Low_Bound => First_Instance_Id, Table_Initial => 16); procedure Resize_Extra_Tables (Id : Instance_Id_Type) is begin while Id > Extra_Tables.Last loop Extra_Tables.Append ((Base => null, Name => No_Sname)); end loop; end Resize_Extra_Tables; procedure Set_Extra (Inst : Synth_Instance_Acc; Extra : Extra_Vhdl_Instance_Type) is Id : constant Instance_Id_Type := Get_Instance_Id (Inst); begin Resize_Extra_Tables (Id); Extra_Tables.Table (Id) := Extra; end Set_Extra; procedure Make_Base_Instance (Base : Base_Instance_Acc) is begin Set_Extra (Root_Instance, (Base => Base, Name => No_Sname)); end Make_Base_Instance; procedure Free_Base_Instance is begin -- TODO: really free. null; end Free_Base_Instance; function Get_Instance_Extra (Inst : Synth_Instance_Acc) return Extra_Vhdl_Instance_Type is begin return Extra_Tables.Table (Get_Instance_Id (Inst)); end Get_Instance_Extra; procedure Set_Extra (Inst : Synth_Instance_Acc; Base : Base_Instance_Acc; Name : Sname := No_Sname) is begin Set_Extra (Inst, (Base => Base, Name => Name)); end Set_Extra; procedure Set_Extra (Inst : Synth_Instance_Acc; Parent : Synth_Instance_Acc; Name : Sname := No_Sname) is Id : constant Instance_Id_Type := Get_Instance_Id (Inst); begin Resize_Extra_Tables (Id); Extra_Tables.Table (Id) := (Base => Get_Instance_Extra (Parent).Base, Name => Name); end Set_Extra; function Make_Instance (Parent : Synth_Instance_Acc; Blk : Node; Name : Sname := No_Sname) return Synth_Instance_Acc is Res : Synth_Instance_Acc; begin Res := Make_Elab_Instance (Parent, Blk, Null_Node); Set_Extra (Res, Parent, Name); return Res; end Make_Instance; procedure Set_Instance_Base (Inst : Synth_Instance_Acc; Base : Base_Instance_Acc) is begin Extra_Tables.Table (Get_Instance_Id (Inst)).Base := Base; end Set_Instance_Base; procedure Set_Instance_Base (Inst : Synth_Instance_Acc; Base : Synth_Instance_Acc) is begin Set_Instance_Base (Inst, Get_Instance_Extra (Base).Base); end Set_Instance_Base; procedure Free_Instance (Synth_Inst : in out Synth_Instance_Acc) is begin if Get_Instance_Id (Synth_Inst) = Extra_Tables.Last then Extra_Tables.Decrement_Last; end if; Free_Elab_Instance (Synth_Inst); end Free_Instance; procedure Set_Instance_Module (Inst : Synth_Instance_Acc; M : Module) is Prev_Base : constant Base_Instance_Acc := Get_Instance_Extra (Inst).Base; Base : Base_Instance_Acc; Self_Inst : Instance; begin Base := new Base_Instance_Type'(Builder => Prev_Base.Builder, 
/*
 *  nextpnr -- Next Generation Place and Route
 *
 *  Copyright (C) 2021  The SymbiFlow Authors.
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#ifndef PHYSICAL_NETLIST_WRITER_H
#define PHYSICAL_NETLIST_WRITER_H

#include "nextpnr.h"

NEXTPNR_NAMESPACE_BEGIN

struct FpgaInterchange
{
    static void read_logical_netlist(Context *ctx, const std::string &filename);
    static void write_physical_netlist(const Context *ctx, const std::string &filename);
};

NEXTPNR_NAMESPACE_END

#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-30 11:38:18 +0000
Alias (Obj, Poff, Ptyp, To_Uns32 (Voff), Eoff)); end Create_Value_Dyn_Alias; function Get_Value_Dyn_Alias_Voff (Val : Value_Acc) return Net is begin return To_Net (Val.D_Voff); end Get_Value_Dyn_Alias_Voff; function Get_Net (Ctxt : Context_Acc; Val : Valtyp) return Net is begin case Val.Val.Kind is when Value_Wire => return Get_Current_Value (Ctxt, Get_Value_Wire (Val.Val)); when Value_Net => return Get_Value_Net (Val.Val); when Value_Alias => declare Res : Net; begin if Val.Val.A_Obj.Kind = Value_Wire then Res := Get_Current_Value (Ctxt, Get_Value_Wire (Val.Val.A_Obj)); return Build2_Extract (Ctxt, Res, Val.Val.A_Off.Net_Off, Val.Typ.W); else pragma Assert (Val.Val.A_Off.Net_Off = 0); return Get_Net (Ctxt, (Val.Typ, Val.Val.A_Obj)); end if; end; when Value_Const => declare N : Net; begin N := To_Net (Val.Val.C_Net); if N = No_Net then N := Get_Net (Ctxt, (Val.Typ, Val.Val.C_Val)); Val.Val.C_Net := To_Uns32 (N); Locations.Set_Location (Get_Net_Parent (N), Get_Location (Val.Val.C_Loc)); end if; return N; end; when Value_Memory => return Get_Memtyp_Net (Ctxt, Get_Memtyp (Val)); when others => raise Internal_Error; end case; end Get_Net; function Is_Static_Val (Val : Value_Acc) return Boolean is begin case Val.Kind is when Value_Memory => return True; when Value_Net | Value_Signal | Value_Dyn_Alias => return False; when Value_Wire => declare W : constant Wire_Id := Get_Value_Wire (Val); begin if Get_Kind (W) = Wire_Variable then return Is_Static_Wire (W); else -- A signal does not have static values. return False; end if; end; when Value_File => return True; when Value_Const => return True; when Value_Alias => return Is_Static_Val (Val.A_Obj); end case; end Is_Static_Val; end Synth.Vhdl_Context;