/* * nextpnr -- Next Generation Place and Route * * Copyright (C) 2021 Symbiflow Authors * * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #include "log.h" #include "nextpnr.h" #include "util.h" #include NEXTPNR_NAMESPACE_BEGIN namespace { bool search_routing_for_placement(Arch *arch, WireId start_wire, CellInfo *cell, IdString cell_pin, bool downhill) { std::queue visit_queue; pool already_visited; visit_queue.push(start_wire); already_visited.insert(start_wire); int iter = 0; while (!visit_queue.empty() && iter++ < 1000) { WireId next = visit_queue.front(); visit_queue.pop(); for (auto bp : arch->getWireBelPins(next)) { if (!arch->isValidBelForCellType(cell->type, bp.bel)) continue; if (!arch->checkBelAvail(bp.bel)) continue; // We need to do a test placement to update the bel pin map arch->bindBel(bp.bel, cell, STRENGTH_FIXED); for (IdString bel_pin : arch->getBelPinsForCellPin(cell, cell_pin)) { if (bel_pin == bp.pin) return true; } // Bel pin doesn't match arch->unbindBel(bp.bel); } auto do_visit = [&](PipId pip) { WireId dst = downhill ? arch->getPipDstWire(pip) : arch->getPipSrcWire(pip); if (already_visited.count(dst)) return; visit_queue.push(dst); already_visited.insert(dst); }; if (downhill) { for (auto pip : arch->getPipsDownhill(next)) do_visit(pip); } else { for (auto pip : arch->getPipsUphill(next)) do_visit(pip); } } return false; } } // namespace void Arch::place_iobufs(WireId pad_wire, NetInfo *net, const dict &tightly_attached_bels, pool *placed_cells) { Context *ctx = getCtx(); for (auto cell_port : tightly_attached_bels) { bool downhill = (cell_port.first->ports.at(cell_port.second).type != PORT_OUT); if (cell_port.first->bel != BelId()) continue; if (search_routing_for_placement(this, pad_wire, cell_port.first, cell_port.second, downhill)) { if (ctx->verbose) log_info("Placed IO cell %s:%s at %s.\n", ctx->nameOf(cell_port.first), ctx->nameOf(cell_port.first->type), ctx->nameOfBel(cell_port.first->bel)); placed_cells->insert(cell_port.first); } } // Also try, on a best-effort basis, to preplace other cells in the macro based on downstream routing. This is // needed for the split INBUF+IBUFCTRL arrangement in the UltraScale+, as just placing the INBUF will result in an // unrouteable site and illegal placement. std::queue place_queue; for (auto pc : *placed_cells) place_queue.push(pc); while (!place_que

python-console
=====
This is the result of a small side project to write a Qt widget that
encapsulates an interactive Python shell.

Quickstart
-----
You should have Qt4 and Python libraries. You will need CMake to build this
project as follows:

1. mkdir build
2. cmake ..
3. make

License
-----
This project is licensed under the [MIT](http://opensource.org/licenses/MIT) license.

rt_ref.port); } } } if (getCtx()->verbose) { log_info("Tightly attached BELs for port %s\n", port_name.c_str(getCtx())); for (auto cell_port : tightly_attached_bels) { log_info(" - %s : %s\n", cell_port.first->name.c_str(getCtx()), cell_port.first->type.c_str(getCtx())); } } NPNR_ASSERT(tightly_attached_bels.erase(port_cell) == 1); pool cell_types_in_io_group; for (auto cell_port : tightly_attached_bels) { NPNR_ASSERT(port_cells.find(cell_port.first->name) == port_cells.end()); cell_types_in_io_group.emplace(cell_port.first->type); } // Get possible placement locations for tightly coupled BELs with // port. pool possible_site_types; for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) { IdString tile_type_name(tile_type.name); for (const BelInfoPOD &bel_info : tile_type.bel_data) { if (bel_info.category != BEL_CATEGORY_LOGIC) { break; } for (IdString cell_type : cell_types_in_io_group) { size_t cell_type_index = get_cell_type_index(cell_type); if (bel_info.category == BEL_CATEGORY_LOGIC && bel_info.pin_map[cell_type_index] != -1) { auto *tile = tile_type_prototypes.at(tile_type_name); const SiteInstInfoPOD &site = chip_info->sites[tile->sites[bel_info.site]]; IdString site_type(site.site_type); if (package_pin_site_types.count(site_type)) { possible_site_types.emplace(site_type); } } } } } if (possible_site_types.empty()) { if (getCtx()->verbose) log_info("Port '%s' has no possible site types, falling back to all types!\n", port_name.c_str(getCtx())); possible_site_types = package_pin_site_types; } if (getCtx()->verbose) { log_info("Possible site types for port %s\n", port_name.c_str(getCtx())); for (IdString site_type : possible_site_types) { log_info(" - %s\n", site_type.c_str(getCtx())); } } auto iter = port_cell->attrs.find(id("PACKAGE_PIN")); if (iter == port_cell->attrs.end()) { iter = port_cell->attrs.find(id("LOC")); if (iter == port_cell->attrs.end()) { log_error("Port '%s' is missing PACKAGE_PIN or LOC property\n", port_cell->name.c_str(getCtx())); } } // dict> package_pin_bels; IdString package_pin_id = id(iter->second.as_string()); auto pin_iter = package_pin_bels.find(package_pin_id); if (pin_iter == package_pin_bels.end()) { log_error("Package pin '%s' not found in part %s\n", package_pin_id.c_str(getCtx()), get_part().c_str()); } NPNR_ASSERT(pin_iter != package_pin_bels.end()); // Select the first BEL from package_bel_pins that is a legal site // type. // // This is likely the most generic (versus specialized) site type. BelId package_bel; for (auto site_type_and_bel : pin_iter->second) { IdString legal_site_type = site_type_and_bel.first; BelId bel = site_type_and_bel.second; if (possible_site_types.count(legal_site_type)) { // FIXME: Need to handle case where a port can be in multiple // modes, but only one of the modes works. package_bel = bel; break; } } if (package_bel == BelId()) { log_info("Failed to find BEL for package pin '%s' in any possible site types:\n", package_pin_id.c_str(getCtx())); for (IdString site_type : possible_site_types) { log_info(" - %s\n", site_type.c_str(getCtx())); } log_error("Failed to find BEL for package pin '%s'\n", package_pin_id.c_str(getCtx())); } if (getCtx()->verbose) { log_info("Binding port %s to BEL %s\n", port_name.c_str(getCtx()), getCtx()->nameOfBel(package_bel)); } pool placed_cells; bindBel(package_bel, port_cell, STRENGTH_FIXED); placed_cells.emplace(port_cell); IdStringRange package_bel_pins = getBelPins(package_bel); IdString pad_pin = get_only_value(package_bel_pins); WireId pad_wire = getBelPinWire(package_bel, pad_pin); place_iobufs(pad_wire, ports[port_pair.first].net, tightly_attached_bels, &placed_cells); for (CellInfo *cell : placed_cells) all_placed_io.insert(cell); } // Check at the end of IO placement, because differential pairs might need P and N sides to both be placed to be // legal. for (CellInfo *cell : all_placed_io) { log_info("%s\n", getCtx()->nameOf(cell)); NPNR_ASSERT(cell->bel != BelId()); if (!isBelLocationValid(cell->bel)) { explain_bel_status(cell->bel); log_error("Tightly bound BEL %s was not valid!\n", nameOfBel(cell->bel)); } } } NEXTPNR_NAMESPACE_END