/* * nextpnr -- Next Generation Place and Route * * Copyright (C) 2018 Claire Xenia Wolf * Copyright (C) 2018 gatecat * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef ECP5_ARCH_H #define ECP5_ARCH_H #include #include #include "base_arch.h" #include "nextpnr_types.h" #include "relptr.h" NEXTPNR_NAMESPACE_BEGIN /**** Everything in this section must be kept in sync with chipdb.py ****/ NPNR_PACKED_STRUCT(struct BelWirePOD { LocationPOD rel_wire_loc; int32_t wire_index; int32_t port; int32_t type; }); NPNR_PACKED_STRUCT(struct BelInfoPOD { RelPtr name; int32_t type; int32_t z; RelSlice bel_wires; }); NPNR_PACKED_STRUCT(struct BelPortPOD { LocationPOD rel_bel_loc; int32_t bel_index; int32_t port; }); NPNR_PACKED_STRUCT(struct PipInfoPOD { LocationPOD rel_src_loc, rel_dst_loc; int32_t src_idx, dst_idx; int32_t timing_class; int16_t tile_type; int8_t pip_type; int8_t padding_0; }); NPNR_PACKED_STRUCT(struct PipLocatorPOD { LocationPOD rel_loc; int32_t index; }); NPNR_PACKED_STRUCT(struct WireInfoPOD { RelPtr name; int32_t type; int32_t tile_wire; RelSlice pips_uphill, pips_downhill; RelSlice bel_pins; }); NPNR_PACKED_STRUCT(struct LocationTypePOD { RelSlice bel_data; RelSlice wire_data; RelSlice pip_data; }); NPNR_PACKED_STRUCT(struct PIOInfoPOD { LocationPOD abs_loc; int32_t bel_index; RelPtr function_name; int16_t bank; int16_t dqsgroup; }); NPNR_PACKED_STRUCT(struct PackagePinPOD { RelPtr name; LocationPOD abs_loc; int32_t bel_index; }); NPNR_PACKED_STRUCT(struct PackageInfoPOD { RelPtr name; RelSlice pin_data; }); NPNR_PACKED_STRUCT(struct TileNamePOD { RelPtr name; int16_t type_idx; int16_t padding; }); NPNR_PACKED_STRUCT(struct TileInfoPOD { RelSlice tile_names; }); enum TapDirection : int8_t { TAP_DIR_LEFT = 0, TAP_DIR_RIGHT = 1 }; enum GlobalQuadrant : int8_t { QUAD_UL = 0, QUAD_UR = 1, QUAD_LL = 2, QUAD_LR = 3, }; NPNR_PACKED_STRUCT(struct GlobalInfoPOD { int16_t tap_col; TapDirection tap_dir; GlobalQuadrant quad; int16_t spine_row; int16_t spine_col; }); NPNR_PACKED_STRUCT(struct CellPropDelayPOD { int32_t from_port; int32_t to_port; int32_t min_delay; int32_t max_delay; }); NPNR_PACKED_STRUCT(struct CellSetupHoldPOD { int32_t sig_port; int32_t clock_port; int32_t min_setup; int32_t max_setup; int32_t min_hold; int32_t max_hold; }); NPNR_PACKED_STRUCT(struct CellTimingPOD { int32_t cell_type; RelSlice prop_delays; RelSlice setup_holds; }); NPNR_PACKED_STRUCT(struct PipDelayPOD { int32_t min_base_delay; int32_t max_base_delay; int32_t min_fanout_adder; int32_t max_fanout_adder; }); NPNR_PACKED_STRUCT(struct SpeedGradePOD { RelSlice cell_timings; RelSlice pip_classes; }); NPNR_PACKED_STRUCT(struct ChipInfoPOD { int32_t width, height; int32_t num_tiles; int32_t const_id_count; RelSlice locations; RelSlice location_type; RelSlice location_glbinfo; RelSlice> tiletype_names; RelSlice package_info; RelSlice pio_info; RelSlice tile_info; RelSlice speed_grades; }); /************************ End of chipdb section. ************************/ struct BelIterator { const ChipInfoPOD *chip; int cursor_index; int cursor_tile; BelIterator operator++() { cursor_index++; while (cursor_tile < chip->num_tiles && cursor_index >= chip->locations[chip->location_type[cursor_tile]].bel_data.ssize()) { cursor_index = 0; cursor_tile++; } return *this; } BelIterator operator++(int) { BelIterator prior(*this); ++(*this); return prior; } bool operator!=(const BelIterator &other) const { return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile; } bool operator==(const BelIterator &other) const { return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile; } BelId operator*() const { BelId ret; ret.location.x = cursor_tile % chip->width; ret.location.y = cursor_tile / chip->width; ret.index = cursor_index; return ret; } }; struct BelRange { BelIterator b, e; BelIterator begin() const { return b; } BelIterator end() const { return e; } }; // ----------------------------------------------------------------------- struct BelPinIterator { const BelPortPOD *ptr = nullptr; Location wire_loc; void operator++() { ptr++; } bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; } BelPin operator*() const { BelPin ret; ret.bel.index = ptr->bel_index; ret.bel.location = wire_loc + ptr->rel_bel_loc; ret.pin.index = ptr->port; return ret; } }; struct BelPinRange { BelPinIterator b, e; BelPinIterator begin() const { return b; } BelPinIterator end() const { return e; } }; // ----------------------------------------------------------------------- struct WireIterator { const ChipInfoPOD *chip; int cursor_index; int cursor_tile; WireIterator operator++() { cursor_index++; while (cursor_tile < chip->num_tiles && cursor_index >= chip->locations[chip->location_type[cursor_tile]].wire_data.ssize()) { cursor_index = 0; cursor_tile++; } return *this; } WireIterator operator++(int) { WireIterator prior(*this); ++(*this); return prior; } bool operator!=(const WireIterator &other) const { return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile; } bool operator==(const WireIterator &other) const { return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile; } WireId operator*() const { WireId ret; ret.location.x = cursor_tile % chip->width; ret.location.y = cursor_tile / chip->width; ret.index = cursor_index; return ret; } }; struct WireRange { WireIterator b, e; WireIterator begin() const { return b; } WireIterator end() const { return e; } }; // ----------------------------------------------------------------------- struct AllPipIterator { const ChipInfoPOD *chip; int cursor_index; int cursor_tile; AllPipIterator operator++() { cursor_index++; while (cursor_tile < chip->num_tiles && cursor_index >= chip->locations[chip->location_type[cursor_tile]].pip_data.ssize()) { cursor_index = 0; cursor_tile++; } return *this; } AllPipIterator operator++(int) { AllPipIterator prior(*this); ++(*this); return prior; } bool operator!=(const AllPipIterator &other) const { return cursor_index != other.cursor_index || cursor_tile != other.cursor_tile; } bool operator==(const AllPipIterator &other) const { return cursor_index == other.cursor_index && cursor_tile == other.cursor_tile; } PipId operator*() const { PipId ret; ret.location.x = cursor_tile % chip->width; ret.location.y = cursor_tile / chip->width; ret.index = cursor_index; return ret; } }; struct AllPipRange { AllPipIterator b, e; AllPipIterator begin() const { return b; } AllPipIterator end() const { return e; } }; // ----------------------------------------------------------------------- struct PipIterator { const PipLocatorPOD *cursor = nullptr; Location wire_loc; void operator++() { cursor++; } bool operator!=(const PipIterator &other) const { return cursor != other.cursor; } PipId operator*() const { PipId ret; ret.index = cursor->index; ret.location = wire_loc + cursor->rel_loc; return ret; } }; struct PipRange { PipIterator b, e; PipIterator begin() const { return b; } PipIterator end() const { return e; } }; struct ArchArgs { enum ArchArgsTypes { NONE, LFE5U_12F, LFE5U_25F, LFE5U_45F, LFE5U_85F, LFE5UM_25F, LFE5UM_45F, LFE5UM_85F, LFE5UM5G_25F, LFE5UM5G_45F, LFE5UM5G_85F, } type = NONE; std::string package; enum SpeedGrade { SPEED_6 = 0, SPEED_7, SPEED_8, SPEED_8_5G, } speed = SPEED_6; }; struct DelayKey { IdString celltype, from, to; inline bool operator==(const DelayKey &other) const { return celltype == other.celltype && from == other.from && to == other.to; } unsigned int hash() const { return mkhash(celltype.hash(), mkhash(from.hash(), to.hash())); } }; struct ArchRanges : BaseArchRanges { using ArchArgsT = ArchArgs; // Bels using AllBelsRangeT = BelRange; using TileBelsRangeT = BelRange; using BelPinsRangeT = std::vector; // Wires using AllWiresRangeT = WireRange; using DownhillPipRangeT = PipRange; using UphillPipRangeT = PipRange; using WireBelPinRangeT = BelPinRange; // Pips using AllPipsRangeT = AllPipRange; }; struct Arch : BaseArch { const ChipInfoPOD *chip_info; const PackageInfoPOD *package_info; const SpeedGradePOD *speed_grade; mutable dict pip_by_name; std::vector bel_to_cell; dict wire_fanout; // fast access to X and Y IdStrings for building object names std::vector x_ids, y_ids; // inverse of the above for name->object mapping dict id_to_x, id_to_y; ArchArgs args; Arch(ArchArgs args); static bool is_available(ArchArgs::ArchArgsTypes chip); static std::vector get_supported_packages(ArchArgs::ArchArgsTypes chip); std::string getChipName() const override; std::string get_full_chip_name() const; ArchArgs archArgs() const override { return args; } IdString archArgsToId(ArchArgs args) const override; // ------------------------------------------------- static const int max_loc_bels = 20; int getGridDimX() const override { return chip_info->width; }; int getGridDimY() const override { return chip_info->height; }; int getTileBelDimZ(int, int) const override { return max_loc_bels; }; int getTilePipDimZ(int, int) const override { return 1; }; char getNameDelimiter() const override { return '/'; } // ------------------------------------------------- BelId getBelByName(IdStringList name) const override; template const LocationTypePOD *loc_info(Id &id) const { return &(chip_info->locations[chip_info->location_type[id.location.y * chip_info->width + id.location.x]]); } IdStringList getBelName(BelId bel) const override { NPNR_ASSERT(bel != BelId()); std::array ids{x_ids.at(bel.location.x), y_ids.at(bel.location.y), id(loc_info(bel)->bel_data[bel.index].name.get())}; return IdStringList(ids); } uint32_t getBelChecksum(BelId bel) const override { return bel.index; } int get_bel_flat_index(BelId bel) const { return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index; } void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override { NPNR_ASSERT(bel != BelId()); int idx = get_bel_flat_index(bel); NPNR_ASSERT(bel_to_cell.at(idx) == nullptr); bel_to_cell[idx] = cell; cell->bel = bel; cell->belStrength = strength; refreshUiBel(bel); } void unbindBel(BelId bel) override { NPNR_ASSERT(bel != BelId()); int idx = get_bel_flat_index(bel); NPNR_ASSERT(bel_to_cell.at(idx) != nullptr); bel_to_cell[idx]->bel = BelId(); bel_to_cell[idx]->belStrength = STRENGTH_NONE; bel_to_cell[idx] = nullptr; refreshUiBel(bel); } Loc getBelLocation(BelId bel) const override { Loc loc; loc.x = bel.location.x; loc.y = bel.location.y; loc.z = loc_info(bel)->bel_data[bel.index].z; return loc; } BelId getBelByLocation(Loc loc) const override; BelRange getBelsByTile(int x, int y) const override; bool getBelGlobalBuf(BelId bel) const override { return getBelType(bel) == id_DCCA; } bool checkBelAvail(BelId bel) const override { NPNR_ASSERT(bel != BelId()); return bel_to_cell[get_bel_flat_index(bel)] == nullptr; } CellInfo *getBoundBelCell(BelId bel) const override { NPNR_ASSERT(bel != BelId()); return bel_to_cell[get_bel_flat_index(bel)]; } CellInfo *getConflictingBelCell(BelId bel) const override { NPNR_ASSERT(bel != BelId()); return bel_to_cell[get_bel_flat_index(bel)]; } BelRange getBels() const override { BelRange range; range.b.cursor_tile = 0; range.b.cursor_index = -1; range.b.chip = chip_info; ++range.b; //-1 and then ++ deals with the case of no Bels in the first tile range.e.cursor_tile = chip_info->width * chip_info->height; range.e.cursor_index = 0; range.e.chip = chip_info; return range; } IdString getBelType(BelId bel) const override { NPNR_ASSERT(bel != BelId()); IdString id; id.index = loc_info(bel)->bel_data[bel.index].type; return id; } WireId getBelPinWire(BelId bel, IdString pin) const override; BelPinRange getWireBelPins(WireId wire) const override { BelPinRange range; NPNR_ASSERT(wire != WireId()); range.b.ptr = loc_info(wire)->wire_data[wire.index].bel_pins.begin(); range.b.wire_loc = wire.location; range.e.ptr = loc_info(wire)->wire_data[wire.index].bel_pins.end(); range.e.wire_loc = wire.location; return range; } std::vector getBelPins(BelId bel) const override; // ------------------------------------------------- WireId getWireByName(IdStringList name) const override; IdStringList getWireName(WireId wire) const override { NPNR_ASSERT(wire != WireId()); std::array ids{x_ids.at(wire.location.x), y_ids.at(wire.location.y), id(loc_info(wire)->wire_data[wire.index].name.get())}; return IdStringList(ids); } IdString getWireType(WireId wire) const override { NPNR_ASSERT(wire != WireId()); IdString id; id.index = loc_info(wire)->wire_data[wire.index].type; return id; } std::vector> getWireAttrs(WireId) const override; uint32_t getWireChecksum(WireId wire) const override { return wire.index; } void unbindWire(WireId wire) override { NPNR_ASSERT(wire != WireId()); NPNR_ASSERT(base_wire2net[wire] != nullptr); auto &net_wires = base_wire2net[wire]->wires; auto it = net_wires.find(wire); NPNR_ASSERT(it != net_wires.end()); auto pip = it->second.pip; // As well as the default rules; need to handle fanout counting if (pip != PipId()) { wire_fanout[getPipSrcWire(pip)]--; } BaseArch::unbindWire(wire); } DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); } WireRange getWires() const override { WireRange range; range.b.cursor_tile = 0; range.b.cursor_index = -1; range.b.chip = chip_info; ++range.b; //-1 and then ++ deals with the case of no wries in the first tile range.e.cursor_tile = chip_info->width * chip_info->height; range.e.cursor_index = 0; range.e.chip = chip_info; return range; } IdString get_wire_basename(WireId wire) const { return id(loc_info(wire)->wire_data[wire.index].name.get()); } WireId get_wire_by_loc_basename(Location loc, std::string basename) const { WireId wireId; wireId.location = loc; for (int i = 0; i < loc_info(wireId)->wire_data.ssize(); i++) { if (loc_info(wireId)->wire_data[i].name.get() == basename) { wireId.index = i; return wireId; } } return WireId(); } // ------------------------------------------------- PipId getPipByName(IdStringList name) const override; IdStringList getPipName(PipId pip) const override; uint32_t getPipChecksum(PipId pip) const override { return pip.index; } void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override { wire_fanout[getPipSrcWire(pip)]++; BaseArch::bindPip(pip, net, strength); } void unbindPip(PipId pip) override { wire_fanout[getPipSrcWire(pip)]--; BaseArch::unbindPip(pip); } AllPipRange getPips() const override { AllPipRange range; range.b.cursor_tile = 0; range.b.cursor_index = -1; range.b.chip = chip_info; ++range.b; //-1 and then ++ deals with the case of no wries in the first tile range.e.cursor_tile = chip_info->width * chip_info->height; range.e.cursor_index = 0; range.e.chip = chip_info; return range; } WireId getPipSrcWire(PipId pip) const override { WireId wire; NPNR_ASSERT(pip != PipId()); wire.index = loc_info(pip)->pip_data[pip.index].src_idx; wire.location = pip.location + loc_info(pip)->pip_data[pip.index].rel_src_loc; return wire; } WireId getPipDstWire(PipId pip) const override { WireId wire; NPNR_ASSERT(pip != PipId()); wire.index = loc_info(pip)->pip_data[pip.index].dst_idx; wire.location = pip.location + loc_info(pip)->pip_data[pip.index].rel_dst_loc; return wire; } DelayQuad getPipDelay(PipId pip) const override { NPNR_ASSERT(pip != PipId()); int fanout = 0; auto fnd_fanout = wire_fanout.find(getPipSrcWire(pip)); if (fnd_fanout != wire_fanout.end()) fanout = fnd_fanout->second; delay_t min_dly = speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_base_delay + fanout * speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_fanout_adder; delay_t max_dly = speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_base_delay + fanout * speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_fanout_adder; return DelayQuad(min_dly, max_dly); } PipRange getPipsDownhill(WireId wire) const override { PipRange range; NPNR_ASSERT(wire != WireId()); range.b.cursor = loc_info(wire)->wire_data[wire.index].pips_downhill.get(); range.b.wire_loc = wire.location; range.e.cursor = range.b.cursor + loc_info(wire)->wire_data[wire.index].pips_downhill.size(); range.e.wire_loc = wire.location; return range; } PipRange getPipsUphill(WireId wire) const override { PipRange range; NPNR_ASSERT(wire != WireId()); range.b.cursor = loc_info(wire)->wire_data[wire.index].pips_uphill.get(); range.b.wire_loc = wire.location; range.e.cursor = range.b.cursor + loc_info(wire)->wire_data[wire.index].pips_uphill.size(); range.e.wire_loc = wire.location; return range; } std::string get_pip_tilename(PipId pip) const { auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x]; for (auto &tn : tileloc.tile_names) { if (tn.type_idx == loc_info(pip)->pip_data[pip.index].tile_type) return tn.name.get(); } NPNR_ASSERT_FALSE("failed to find Pip tile"); } std::string get_pip_tiletype(PipId pip) const { return chip_info->tiletype_names[loc_info(pip)->pip_data[pip.index].tile_type].get(); } Loc getPipLocation(PipId pip) const override { Loc loc; loc.x = pip.location.x; loc.y = pip.location.y; loc.z = 0; return loc; } int8_t get_pip_class(PipId pip) const { return loc_info(pip)->pip_data[pip.index].pip_type; } BelId get_package_pin_bel(const std::string &pin) const; std::string get_bel_package_pin(BelId bel) const; int get_pio_bel_bank(BelId bel) const; // For getting GCLK, PLL, Vref, etc, pins std::string get_pio_function_name(BelId bel) const; BelId get_pio_by_function_name(const std::string &name) const; PortType getBelPinType(BelId bel, IdString pin) const override; // ------------------------------------------------- GroupId getGroupByName(IdStringList name) const override; IdStringList getGroupName(GroupId group) const override; std::vector getGroups() const override; std::vector getGroupBels(GroupId group) const override; std::vector getGroupWires(GroupId group) const override; std::vector getGroupPips(GroupId group) const override; std::vector getGroupGroups(GroupId group) const override; // ------------------------------------------------- delay_t estimateDelay(WireId src, WireId dst) const override; ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override; delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override; delay_t getDelayEpsilon() const override { return 20; } delay_t getRipupDelayPenalty() const override; float getDelayNS(delay_t v) const override { return v * 0.001; } delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); } uint32_t getDelayChecksum(delay_t v) const override { return v; } bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override; // ------------------------------------------------- bool pack() override; bool place() override; bool route() override; // ------------------------------------------------- std::vector getDecalGraphics(DecalId decal) const override; DecalXY getBelDecal(BelId bel) const override; DecalXY getWireDecal(WireId wire) const override; DecalXY getPipDecal(PipId pip) const override; DecalXY getGroupDecal(GroupId group) const override; // ------------------------------------------------- // Get the delay through a cell from one port to another, returning false // if no path exists bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override; // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override; // Get the TimingClockingInfo of a port TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override; // Return true if a port is a net bool is_global_net(const NetInfo *net) const; bool get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, DelayQuad &delay) const; void get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString port, DelayPair &setup, DelayPair &hold) const; // ------------------------------------------------- // Placement validity checks bool isBelLocationValid(BelId bel) const override; // Helper function for above bool slices_compatible(const std::vector &cells) const; void assignArchInfo() override; void permute_luts(); std::vector> get_tiles_at_loc(int row, int col); std::string get_tile_by_type_loc(int row, int col, std::string type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; for (auto &tn : tileloc.tile_names) { if (chip_info->tiletype_names[tn.type_idx].get() == type) return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type " + type); } std::string get_tile_by_type_loc(int row, int col, const std::set &type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; for (auto &tn : tileloc.tile_names) { if (type.count(chip_info->tiletype_names[tn.type_idx].get())) return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set"); } std::string get_tile_by_type(std::string type) const { for (int i = 0; i < chip_info->height * chip_info->width; i++) { auto &tileloc = chip_info->tile_info[i]; for (auto &tn : tileloc.tile_names) if (chip_info->tiletype_names[tn.type_idx].get() == type) return tn.name.get(); } NPNR_ASSERT_FALSE_STR("no tile with type " + type); } GlobalInfoPOD global_info_at_loc(Location loc); bool get_pio_dqs_group(BelId pio, bool &dqsright, int &dqsrow); BelId get_dqsbuf(bool dqsright, int dqsrow); WireId get_bank_eclk(int bank, int eclk); // Apply LPF constraints to the context bool apply_lpf(std::string filename, std::istream &in); IdString id_trellis_slice; IdString id_clk, id_lsr; IdString id_clkmux, id_lsrmux; IdString id_srmode, id_mode; // Special case for delay estimates due to its physical location // being far from the logical location of its primitive WireId gsrclk_wire; // Improves directivity of routing to DSP inputs, avoids issues // with different routes to the same physical reset wire causing // conflicts and slow routing dict> wire_loc_overrides; void setup_wire_locations(); mutable dict> celldelay_cache; static const std::string defaultPlacer; static const std::vector availablePlacers; static const std::string defaultRouter; static const std::vector availableRouters; std::vector cell_types; std::vector buckets; }; NEXTPNR_NAMESPACE_END #endif /* ECP5_ARCH_H */ id='n732' href='#n732'>732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562