From e260ac33abdd175f38ea5d8367c52a154b486648 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 7 Dec 2022 10:00:53 +0100 Subject: refactor: ArcBounds -> BoundingBox Signed-off-by: gatecat --- mistral/arch.cc | 4 ++-- mistral/arch.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'mistral') diff --git a/mistral/arch.cc b/mistral/arch.cc index 4023f5c3..ce4f93fb 100644 --- a/mistral/arch.cc +++ b/mistral/arch.cc @@ -435,9 +435,9 @@ void Arch::assignArchInfo() } } -ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const +BoundingBox Arch::getRouteBoundingBox(WireId src, WireId dst) const { - ArcBounds bounds; + BoundingBox bounds; int src_x = CycloneV::rn2x(src.node); int src_y = CycloneV::rn2y(src.node); int dst_x = CycloneV::rn2x(dst.node); diff --git a/mistral/arch.h b/mistral/arch.h index 5ceda53c..54a39771 100644 --- a/mistral/arch.h +++ b/mistral/arch.h @@ -425,7 +425,7 @@ struct Arch : BaseArch delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000.0f); }; uint32_t getDelayChecksum(delay_t v) const override { return v; }; - ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override; + BoundingBox getRouteBoundingBox(WireId src, WireId dst) const override; TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override; // delay.cc -- cgit v1.2.3