From fd2174149c3e4654dbe1571e129fadb312f29c33 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 3 Aug 2018 16:29:44 +0200
Subject: Fixing constraint placement bugs

Signed-off-by: David Shah <davey1576@gmail.com>
---
 ice40/chains.cc | 6 +++++-
 ice40/gfx.cc    | 3 ++-
 ice40/pack.cc   | 5 +++--
 3 files changed, 10 insertions(+), 4 deletions(-)

(limited to 'ice40')

diff --git a/ice40/chains.cc b/ice40/chains.cc
index 54e284af..dce27863 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -278,6 +278,10 @@ class ChainConstrainer
     void constrain_chains() { process_carries(); }
 };
 
-void constrain_chains(Context *ctx) { log_info("Constraining chains...\n"); ChainConstrainer(ctx).constrain_chains(); }
+void constrain_chains(Context *ctx)
+{
+    log_info("Constraining chains...\n");
+    ChainConstrainer(ctx).constrain_chains();
+}
 
 NEXTPNR_NAMESPACE_END
diff --git a/ice40/gfx.cc b/ice40/gfx.cc
index 924fe964..d5c6e77f 100644
--- a/ice40/gfx.cc
+++ b/ice40/gfx.cc
@@ -706,7 +706,8 @@ void gfxTilePip(std::vector<GraphicElement> &g, int x, int y, GfxTileWireId src,
         return;
     }
 
-    if (TILE_WIRE_LUTFF_0_IN_0 <= src && src <= TILE_WIRE_LUTFF_7_IN_3 && TILE_WIRE_LUTFF_0_OUT <= dst && dst <= TILE_WIRE_LUTFF_7_OUT) {
+    if (TILE_WIRE_LUTFF_0_IN_0 <= src && src <= TILE_WIRE_LUTFF_7_IN_3 && TILE_WIRE_LUTFF_0_OUT <= dst &&
+        dst <= TILE_WIRE_LUTFF_7_OUT) {
         int lut_idx = (src - TILE_WIRE_LUTFF_0_IN_0) / 4;
         int in_idx = (src - TILE_WIRE_LUTFF_0_IN_0) % 4;
 
diff --git a/ice40/pack.cc b/ice40/pack.cc
index 9700bc5d..e7fdc627 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -23,10 +23,10 @@
 #include <iterator>
 #include <unordered_set>
 #include "cells.h"
+#include "chains.h"
 #include "design_utils.h"
 #include "log.h"
 #include "util.h"
-#include "chains.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -445,7 +445,8 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port)
 {
     if (is_clock_port(ctx, port) || is_reset_port(ctx, port) || is_enable_port(ctx, port))
         return false;
-    return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) && port.cell->type != ctx->id("SB_GB");
+    return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) &&
+           port.cell->type != ctx->id("SB_GB");
 }
 
 static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic)
-- 
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