From c60fb94b6c45ca74632e972995555170063b3a03 Mon Sep 17 00:00:00 2001 From: gatecat Date: Wed, 10 Aug 2022 18:58:22 +0100 Subject: refactor: Use IdString::in instead of || chains Signed-off-by: gatecat --- ice40/arch.cc | 36 ++++++++++++++++++------------------ ice40/arch_place.cc | 2 +- ice40/bitstream.cc | 3 +-- ice40/cells.cc | 8 ++++---- ice40/cells.h | 20 +++++++------------- ice40/pack.cc | 8 ++++---- 6 files changed, 35 insertions(+), 42 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 905b8d61..c9c99d3a 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -643,7 +643,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay { const auto &driver = net_info->driver; if (driver.port == id_COUT) { - NPNR_ASSERT(sink.port == id_CIN || sink.port == id_I3); + NPNR_ASSERT(sink.port.in(id_CIN, id_I3)); NPNR_ASSERT(driver.cell->constr_abs_z); bool cin = sink.port == id_CIN; bool same_y = driver.cell->constr_z < 7; @@ -904,7 +904,7 @@ std::vector Arch::getDecalGraphics(DecalId decal) const ret.push_back(el); } - if (bel_type == id_ICESTORM_PLL || bel_type == id_SB_WARMBOOT) { + if (bel_type.in(id_ICESTORM_PLL, id_SB_WARMBOOT)) { GraphicElement el; el.type = GraphicElement::TYPE_BOX; el.style = decal.active ? GraphicElement::STYLE_ACTIVE : GraphicElement::STYLE_INACTIVE; @@ -937,7 +937,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort if (fromPort == id_I3 && ((cell->lcInfo.lutInputMask & 0x8U) == 0)) return false; } - } else if (cell->type == id_ICESTORM_RAM || cell->type == id_ICESTORM_SPRAM) { + } else if (cell->type.in(id_ICESTORM_RAM, id_ICESTORM_SPRAM)) { return false; } return get_cell_delay_internal(cell, fromPort, toPort, delay); @@ -971,7 +971,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_CLOCK_INPUT; if (port == id_CIN) return TMG_COMB_INPUT; - if (port == id_COUT || port == id_LO) + if (port.in(id_COUT, id_LO)) return TMG_COMB_OUTPUT; if (port == id_O) { // LCs with no inputs are constant drivers @@ -991,7 +991,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } } else if (cell->type == id_ICESTORM_RAM) { - if (port == id_RCLK || port == id_WCLK) + if (port.in(id_RCLK, id_WCLK)) return TMG_CLOCK_INPUT; clockInfoCount = 1; @@ -1000,8 +1000,8 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_REGISTER_OUTPUT; else return TMG_REGISTER_INPUT; - } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) { - if (port == id_CLK || port == id_CLOCK) + } else if (cell->type.in(id_ICESTORM_DSP, id_ICESTORM_SPRAM)) { + if (port.in(id_CLK, id_CLOCK)) return TMG_CLOCK_INPUT; else { clockInfoCount = 1; @@ -1011,7 +1011,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_REGISTER_INPUT; } } else if (cell->type == id_SB_IO) { - if (port == id_INPUT_CLK || port == id_OUTPUT_CLK) + if (port.in(id_INPUT_CLK, id_OUTPUT_CLK)) return TMG_CLOCK_INPUT; if (port == id_CLOCK_ENABLE) { clockInfoCount = 2; @@ -1023,7 +1023,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in } else if (port == id_D_IN_0) { return TMG_STARTPOINT; } - if (port == id_D_OUT_0 || port == id_D_OUT_1) { + if (port.in(id_D_OUT_0, id_D_OUT_1)) { if ((cell->ioInfo.pintype & 0xC) == 0x8) { return TMG_ENDPOINT; } else { @@ -1041,7 +1041,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_IGNORE; } else if (cell->type == id_ICESTORM_PLL) { - if (port == id_PLLOUT_A || port == id_PLLOUT_B || port == id_PLLOUT_A_GLOBAL || port == id_PLLOUT_B_GLOBAL) + if (port.in(id_PLLOUT_A, id_PLLOUT_B, id_PLLOUT_A_GLOBAL, id_PLLOUT_B_GLOBAL)) return TMG_GEN_CLOCK; return TMG_IGNORE; } else if (cell->type == id_ICESTORM_LFOSC) { @@ -1063,18 +1063,18 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return TMG_IGNORE; return TMG_ENDPOINT; } else if (cell->type == id_SB_RGB_DRV) { - if (port == id_RGB0 || port == id_RGB1 || port == id_RGB2 || port == id_RGBPU) + if (port.in(id_RGB0, id_RGB1, id_RGB2, id_RGBPU)) return TMG_IGNORE; return TMG_ENDPOINT; } else if (cell->type == id_SB_RGBA_DRV) { - if (port == id_RGB0 || port == id_RGB1 || port == id_RGB2) + if (port.in(id_RGB0, id_RGB1, id_RGB2)) return TMG_IGNORE; return TMG_ENDPOINT; } else if (cell->type == id_SB_LEDDA_IP) { - if (port == id_CLK || port == id_CLOCK) + if (port.in(id_CLK, id_CLOCK)) return TMG_CLOCK_INPUT; return TMG_IGNORE; - } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) { + } else if (cell->type.in(id_SB_I2C, id_SB_SPI)) { if (port == id_SBCLKI) return TMG_CLOCK_INPUT; @@ -1098,7 +1098,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port bool has_clktoq = get_cell_delay_internal(cell, id_CLK, id_O, info.clockToQ); NPNR_ASSERT(has_clktoq); } else { - if (port == id_I0 || port == id_I1 || port == id_I2 || port == id_I3) { + if (port.in(id_I0, id_I1, id_I2, id_I3)) { DelayQuad dlut; bool has_ld = get_cell_delay_internal(cell, port, id_O, dlut); NPNR_ASSERT(has_ld); @@ -1146,7 +1146,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE; info.setup = DelayPair(io_setup); info.hold = DelayPair(0); - } else if (port == id_D_OUT_0 || port == id_OUTPUT_ENABLE) { + } else if (port.in(id_D_OUT_0, id_OUTPUT_ENABLE)) { info.clock_port = id_OUTPUT_CLK; info.edge = cell->ioInfo.negtrig ? FALLING_EDGE : RISING_EDGE; info.setup = DelayPair(io_setup); @@ -1167,7 +1167,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port } else { NPNR_ASSERT_FALSE("no clock data for IO cell port"); } - } else if (cell->type == id_ICESTORM_DSP || cell->type == id_ICESTORM_SPRAM) { + } else if (cell->type.in(id_ICESTORM_DSP, id_ICESTORM_SPRAM)) { info.clock_port = cell->type == id_ICESTORM_SPRAM ? id_CLOCK : id_CLK; info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { @@ -1178,7 +1178,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port info.setup = DelayPair(100); info.hold = DelayPair(0); } - } else if (cell->type == id_SB_I2C || cell->type == id_SB_SPI) { + } else if (cell->type.in(id_SB_I2C, id_SB_SPI)) { info.clock_port = id_SBCLKI; info.edge = RISING_EDGE; if (cell->ports.at(port).type == PORT_OUT) { diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 67ddf777..5c3fa3c5 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -105,7 +105,7 @@ bool Arch::isBelLocationValid(BelId bel) const // that are a PLL clock output. auto wire = getBelPinWire(bel, id_D_IN_0); for (auto pin : getWireBelPins(wire)) { - if (pin.pin == id_PLLOUT_A || pin.pin == id_PLLOUT_B) { + if (pin.pin.in(id_PLLOUT_A, id_PLLOUT_B)) { // Is there a PLL there ? const CellInfo *pll_cell = getBoundBelCell(pin.bel); if (pll_cell == nullptr) diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 48fbc132..3e50c065 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -640,8 +640,7 @@ void write_asc(const Context *ctx, std::ostream &out) {"CURRENT_MODE", 1}, {"RGB0_CURRENT", 6}, {"RGB1_CURRENT", 6}, {"RGB2_CURRENT", 6}}; configure_extra_cell(config, ctx, cell.second.get(), rgba_params, true, std::string("IpConfig.")); set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "RGBA_DRV_EN", true, "IpConfig."); - } else if (cell.second->type == id_SB_WARMBOOT || cell.second->type == id_ICESTORM_LFOSC || - cell.second->type == id_SB_LEDDA_IP) { + } else if (cell.second->type.in(id_SB_WARMBOOT, id_ICESTORM_LFOSC, id_SB_LEDDA_IP)) { // No config needed } else if (cell.second->type == id_SB_I2C) { bool sda_in_dly = !cell.second->attrs.count(id_SDA_INPUT_DELAYED) || diff --git a/ice40/cells.cc b/ice40/cells.cc index 9166b41b..fc24caaf 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -502,13 +502,13 @@ bool is_clock_port(const BaseCtx *ctx, const PortRef &port) if (port.cell->type == id_ICESTORM_LC) return port.port == id_CLK; if (is_ram(ctx, port.cell) || port.cell->type == id_ICESTORM_RAM) - return port.port == id_RCLK || port.port == id_WCLK || port.port == id_RCLKN || port.port == id_WCLKN; + return port.port.in(id_RCLK, id_WCLK, id_RCLKN, id_WCLKN); if (is_sb_mac16(ctx, port.cell) || port.cell->type == id_ICESTORM_DSP) return port.port == id_CLK; if (is_sb_spram(ctx, port.cell) || port.cell->type == id_ICESTORM_SPRAM) return port.port == id_CLOCK; if (is_sb_io(ctx, port.cell)) - return port.port == id_INPUT_CLK || port.port == id_OUTPUT_CLK; + return port.port.in(id_INPUT_CLK, id_OUTPUT_CLK); return false; } @@ -517,11 +517,11 @@ bool is_reset_port(const BaseCtx *ctx, const PortRef &port) if (port.cell == nullptr) return false; if (is_ff(ctx, port.cell)) - return port.port == id_R || port.port == id_S; + return port.port.in(id_R, id_S); if (port.cell->type == id_ICESTORM_LC) return port.port == id_SR; if (is_sb_mac16(ctx, port.cell) || port.cell->type == id_ICESTORM_DSP) - return port.port == id_IRSTTOP || port.port == id_IRSTBOT || port.port == id_ORSTTOP || port.port == id_ORSTBOT; + return port.port.in(id_IRSTTOP, id_IRSTBOT, id_ORSTTOP, id_ORSTBOT); return false; } diff --git a/ice40/cells.h b/ice40/cells.h index 724500d6..8aed649d 100644 --- a/ice40/cells.h +++ b/ice40/cells.h @@ -35,13 +35,9 @@ inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type // Return true if a cell is a flipflop inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { - return cell->type == id_SB_DFF || cell->type == id_SB_DFFE || cell->type == id_SB_DFFSR || - cell->type == id_SB_DFFR || cell->type == id_SB_DFFSS || cell->type == id_SB_DFFS || - cell->type == id_SB_DFFESR || cell->type == id_SB_DFFER || cell->type == id_SB_DFFESS || - cell->type == id_SB_DFFES || cell->type == id_SB_DFFN || cell->type == id_SB_DFFNE || - cell->type == id_SB_DFFNSR || cell->type == id_SB_DFFNR || cell->type == id_SB_DFFNSS || - cell->type == id_SB_DFFNS || cell->type == id_SB_DFFNESR || cell->type == id_SB_DFFNER || - cell->type == id_SB_DFFNESS || cell->type == id_SB_DFFNES; + return cell->type.in(id_SB_DFF, id_SB_DFFE, id_SB_DFFSR, id_SB_DFFR, id_SB_DFFSS, id_SB_DFFS, id_SB_DFFESR, + id_SB_DFFER, id_SB_DFFESS, id_SB_DFFES, id_SB_DFFN, id_SB_DFFNE, id_SB_DFFNSR, id_SB_DFFNR, + id_SB_DFFNSS, id_SB_DFFNS, id_SB_DFFNESR, id_SB_DFFNER, id_SB_DFFNESS, id_SB_DFFNES); } inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_CARRY; } @@ -60,8 +56,7 @@ inline bool is_gbuf(const BaseCtx *ctx, const CellInfo *cell) { return cell->typ // Return true if a cell is a RAM inline bool is_ram(const BaseCtx *ctx, const CellInfo *cell) { - return cell->type == id_SB_RAM40_4K || cell->type == id_SB_RAM40_4KNR || cell->type == id_SB_RAM40_4KNW || - cell->type == id_SB_RAM40_4KNRNW; + return cell->type.in(id_SB_RAM40_4K, id_SB_RAM40_4KNR, id_SB_RAM40_4KNW, id_SB_RAM40_4KNRNW); } inline bool is_sb_lfosc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_SB_LFOSC; } @@ -86,13 +81,12 @@ inline bool is_sb_spi(const BaseCtx *ctx, const CellInfo *cell) { return cell->t inline bool is_sb_pll40(const BaseCtx *ctx, const CellInfo *cell) { - return cell->type == id_SB_PLL40_PAD || cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD || - cell->type == id_SB_PLL40_CORE || cell->type == id_SB_PLL40_2F_CORE; + return cell->type.in(id_SB_PLL40_PAD, id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD, id_SB_PLL40_CORE, id_SB_PLL40_2F_CORE); } inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell) { - return cell->type == id_SB_PLL40_PAD || cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD || + return cell->type.in(id_SB_PLL40_PAD, id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD) || (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_PAD" || cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2_PAD" || cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_PAD")); @@ -100,7 +94,7 @@ inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell) inline bool is_sb_pll40_dual(const BaseCtx *ctx, const CellInfo *cell) { - return cell->type == id_SB_PLL40_2_PAD || cell->type == id_SB_PLL40_2F_PAD || cell->type == id_SB_PLL40_2F_CORE || + return cell->type.in(id_SB_PLL40_2_PAD, id_SB_PLL40_2F_PAD, id_SB_PLL40_2F_CORE) || (cell->type == id_ICESTORM_PLL && (cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2_PAD" || cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_PAD" || cell->attrs.at(id_TYPE).as_string() == "SB_PLL40_2F_CORE")); diff --git a/ice40/pack.cc b/ice40/pack.cc index 9eff053e..c9811721 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -345,8 +345,8 @@ static void pack_ram(Context *ctx) packed->attrs[attr.first] = attr.second; for (auto param : ci->params) packed->params[param.first] = param.second; - packed->params[id_NEG_CLK_W] = Property(ci->type == id_SB_RAM40_4KNW || ci->type == id_SB_RAM40_4KNRNW, 1); - packed->params[id_NEG_CLK_R] = Property(ci->type == id_SB_RAM40_4KNR || ci->type == id_SB_RAM40_4KNRNW, 1); + packed->params[id_NEG_CLK_W] = Property(ci->type.in(id_SB_RAM40_4KNW, id_SB_RAM40_4KNRNW), 1); + packed->params[id_NEG_CLK_R] = Property(ci->type.in(id_SB_RAM40_4KNR, id_SB_RAM40_4KNRNW), 1); packed->type = id_ICESTORM_RAM; for (auto port : ci->ports) { PortInfo &pi = port.second; @@ -1468,11 +1468,11 @@ void pack_plls(Context *ctx) newname = newname.substr(0, bpos) + "_" + newname.substr(bpos + 1, (newname.size() - bpos) - 2); } - if (pi.name == id_PLLOUTCOREA || pi.name == id_PLLOUTCORE) + if (pi.name.in(id_PLLOUTCOREA, id_PLLOUTCORE)) newname = "PLLOUT_A"; if (pi.name == id_PLLOUTCOREB) newname = "PLLOUT_B"; - if (pi.name == id_PLLOUTGLOBALA || pi.name == id_PLLOUTGLOBAL) + if (pi.name.in(id_PLLOUTGLOBALA, id_PLLOUTGLOBAL)) newname = "PLLOUT_A_GLOBAL"; if (pi.name == id_PLLOUTGLOBALB) newname = "PLLOUT_B_GLOBAL"; -- cgit v1.2.3