From 59a790cd00421d14120927fbb1718da8cd77e3c4 Mon Sep 17 00:00:00 2001 From: Serge Bazanski Date: Sat, 14 Jul 2018 20:24:20 +0100 Subject: Refactor IdString functionality into IdStringDB This lets us more precisely control the lifetime of IdString databases in contexts/arches. --- ice40/arch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index adc37dbd..c9cda40d 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -102,7 +102,7 @@ BelType Arch::belTypeFromId(IdString type) const // ----------------------------------------------------------------------- -void IdString::initialize_arch(const BaseCtx *ctx) +void IdString::initialize_arch(const IdStringDB *ctx) { #define X(t) initialize_add(ctx, #t, PIN_##t); #include "portpins.inc" -- cgit v1.2.3 From 03508faabfc2f5b76039cfd13d02a341baa848a4 Mon Sep 17 00:00:00 2001 From: Serge Bazanski Date: Tue, 17 Jul 2018 19:16:26 +0100 Subject: WIP. --- ice40/arch.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'ice40') diff --git a/ice40/arch.h b/ice40/arch.h index 5dab414b..b89a0b54 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -373,6 +373,7 @@ struct Arch : BaseCtx bel_to_cell[bel.index] = cell; cells[cell]->bel = bel; cells[cell]->belStrength = strength; + refreshUiBel(bel); } void unbindBel(BelId bel) @@ -382,6 +383,7 @@ struct Arch : BaseCtx cells[bel_to_cell[bel.index]]->bel = BelId(); cells[bel_to_cell[bel.index]]->belStrength = STRENGTH_NONE; bel_to_cell[bel.index] = IdString(); + refreshUiBel(bel); } bool checkBelAvail(BelId bel) const @@ -475,6 +477,7 @@ struct Arch : BaseCtx wire_to_net[wire.index] = net; nets[net]->wires[wire].pip = PipId(); nets[net]->wires[wire].strength = strength; + refreshUiWire(wire); } void unbindWire(WireId wire) @@ -494,6 +497,7 @@ struct Arch : BaseCtx net_wires.erase(it); wire_to_net[wire.index] = IdString(); + refreshUiWire(wire); } bool checkWireAvail(WireId wire) const @@ -541,6 +545,8 @@ struct Arch : BaseCtx wire_to_net[dst.index] = net; nets[net]->wires[dst].pip = pip; nets[net]->wires[dst].strength = strength; + refreshUiPip(pip); + refreshUiWire(dst); } void unbindPip(PipId pip) @@ -557,6 +563,8 @@ struct Arch : BaseCtx pip_to_net[pip.index] = IdString(); switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString(); + refreshUiPip(pip); + refreshUiWire(dst); } bool checkPipAvail(PipId pip) const -- cgit v1.2.3 From 76e5236fb3c161a860b2c494fe44fde3011670af Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Fri, 20 Jul 2018 18:24:16 +0100 Subject: Nuke IdStringDB --- ice40/arch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index d1400a63..786d8ba1 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -102,7 +102,7 @@ BelType Arch::belTypeFromId(IdString type) const // ----------------------------------------------------------------------- -void IdString::initialize_arch(const IdStringDB *ctx) +void IdString::initialize_arch(const BaseCtx *ctx) { #define X(t) initialize_add(ctx, #t, PIN_##t); #include "portpins.inc" -- cgit v1.2.3 From 5d0dbe9db961f6dbd2494bd8ab730d8926d01626 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Fri, 20 Jul 2018 18:24:34 +0100 Subject: clang-format --- ice40/arch.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 786d8ba1..64a2a4be 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -19,13 +19,13 @@ #include #include +#include "cells.h" #include "gfx.h" #include "log.h" #include "nextpnr.h" #include "placer1.h" #include "router1.h" #include "util.h" -#include "cells.h" NEXTPNR_NAMESPACE_BEGIN // ----------------------------------------------------------------------- -- cgit v1.2.3 From be14e161ae1963203e380bfbe02cfaeda828f838 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Fri, 20 Jul 2018 18:35:42 +0100 Subject: Re-enable drawing Pips. --- ice40/arch.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 64a2a4be..e09f26be 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -484,9 +484,9 @@ DecalXY Arch::getWireDecal(WireId wire) const DecalXY Arch::getPipDecal(PipId pip) const { DecalXY decalxy; - // decalxy.decal.type = DecalId::TYPE_PIP; - // decalxy.decal.index = pip.index; - // decalxy.decal.active = pip_to_net.at(pip.index) != IdString(); + decalxy.decal.type = DecalId::TYPE_PIP; + decalxy.decal.index = pip.index; + decalxy.decal.active = pip_to_net.at(pip.index) != IdString(); return decalxy; }; -- cgit v1.2.3 From 30e2f0e1e8cfdb24abe6c3a8013691497c706975 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 21 Jul 2018 21:40:06 +0200 Subject: Add Loc constructors Signed-off-by: Clifford Wolf --- ice40/arch.cc | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index e9a7d2b6..bbed4000 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -279,12 +279,7 @@ BelRange Arch::getBelsByTile(int x, int y) const // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used BelRange br; - Loc loc; - loc.x = x; - loc.y = y; - loc.z = 0; - - br.b.cursor = Arch::getBelByLocation(loc).index; + br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index; br.e.cursor = br.b.cursor; if (br.e.cursor != -1) { -- cgit v1.2.3 From 1e96999863da24021c215a3706b5a442789ba3a7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 00:50:49 +0200 Subject: clangformat Signed-off-by: Clifford Wolf --- ice40/arch.cc | 3 +-- ice40/arch.h | 5 +---- ice40/main.cc | 4 ++-- 3 files changed, 4 insertions(+), 8 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 5d7d1fb4..3833dcb7 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -283,8 +283,7 @@ BelRange Arch::getBelsByTile(int x, int y) const br.e.cursor = br.b.cursor; if (br.e.cursor != -1) { - while (br.e.cursor < chip_info->num_bels && - chip_info->bel_data[br.e.cursor].x == x && + while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x && chip_info->bel_data[br.e.cursor].y == y) br.e.cursor++; } diff --git a/ice40/arch.h b/ice40/arch.h index b7e66414..9a8ec7bc 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -455,10 +455,7 @@ struct Arch : BaseCtx BelId getBelByLocation(Loc loc) const; BelRange getBelsByTile(int x, int y) const; - bool getBelGlobalBuf(BelId bel) const - { - return chip_info->bel_data[bel.index].type == TYPE_SB_GB; - } + bool getBelGlobalBuf(BelId bel) const { return chip_info->bel_data[bel.index].type == TYPE_SB_GB; } BelRange getBelsAtSameTile(BelId bel) const NPNR_DEPRECATED; diff --git a/ice40/main.cc b/ice40/main.cc index 70324a91..b84d6d92 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -69,8 +69,8 @@ void svg_dump_decal(const Context *ctx, const DecalXY &decal) void conflicting_options(const boost::program_options::variables_map &vm, const char *opt1, const char *opt2) { if (vm.count(opt1) && !vm[opt1].defaulted() && vm.count(opt2) && !vm[opt2].defaulted()) { - std::string msg = "Conflicting options '"+ std::string(opt1) + "' and '" + std::string(opt1) + "'."; - log_error("%s\n",msg.c_str()); + std::string msg = "Conflicting options '" + std::string(opt1) + "' and '" + std::string(opt1) + "'."; + log_error("%s\n", msg.c_str()); } } -- cgit v1.2.3 From 62b66e02085371c456dee95dc08d2cd41351c91f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 10:59:21 +0200 Subject: Rename getWireBelPin to getBelPinWire Signed-off-by: Clifford Wolf --- ice40/arch.cc | 2 +- ice40/arch.h | 2 +- ice40/arch_place.cc | 2 +- ice40/arch_pybindings.cc | 4 ++-- ice40/bitstream.cc | 6 +++--- ice40/main.cc | 20 ++++++++++---------- 6 files changed, 18 insertions(+), 18 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 3833dcb7..a670f286 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -308,7 +308,7 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const return br; } -WireId Arch::getWireBelPin(BelId bel, PortPin pin) const +WireId Arch::getBelPinWire(BelId bel, PortPin pin) const { WireId ret; diff --git a/ice40/arch.h b/ice40/arch.h index 9a8ec7bc..566f807a 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -465,7 +465,7 @@ struct Arch : BaseCtx return chip_info->bel_data[bel.index].type; } - WireId getWireBelPin(BelId bel, PortPin pin) const; + WireId getBelPinWire(BelId bel, PortPin pin) const; BelPin getBelPinUphill(WireId wire) const { diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 116ab7d3..cf1276a7 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -110,7 +110,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const } else if (cell->type == id_sb_gb) { NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr); const NetInfo *net = cell->ports.at(id_glb_buf_out).net; - IdString glb_net = getWireName(getWireBelPin(bel, PIN_GLOBAL_BUFFER_OUTPUT)); + IdString glb_net = getWireName(getBelPinWire(bel, PIN_GLOBAL_BUFFER_OUTPUT)); int glb_id = std::stoi(std::string("") + glb_net.str(this).back()); if (net->is_reset && net->is_enable) return false; diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc index fd5109b4..a1ce9f5b 100644 --- a/ice40/arch_pybindings.cc +++ b/ice40/arch_pybindings.cc @@ -82,8 +82,8 @@ void arch_wrap_python() fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getBelsAtSameTile"); - fn_wrapper_2a, - conv_from_str, conv_from_str>::def_wrap(ctx_cls, "getWireBelPin"); + fn_wrapper_2a, + conv_from_str, conv_from_str>::def_wrap(ctx_cls, "getBelPinWire"); fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getBelPinUphill"); fn_wrapper_1awire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_0).index] != IdString()) || - (ctx->wire_to_net[ctx->getWireBelPin(bel, PIN_D_IN_1).index] != IdString())) { + if ((ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_0).index] != IdString()) || + (ctx->wire_to_net[ctx->getBelPinWire(bel, PIN_D_IN_1).index] != IdString())) { input_en = true; } @@ -762,7 +762,7 @@ bool read_asc(Context *ctx, std::istream &in) if (cell.second->bel != BelId()) { for (auto &port : cell.second->ports) { PortPin pin = ctx->portPinFromId(port.first); - WireId wire = ctx->getWireBelPin(cell.second->bel, pin); + WireId wire = ctx->getBelPinWire(cell.second->bel, pin); if (wire != WireId()) { IdString name = ctx->getBoundWireNet(wire); if (name != IdString()) { diff --git a/ice40/main.cc b/ice40/main.cc index b84d6d92..24b49184 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -322,25 +322,25 @@ int main(int argc, char *argv[]) src_wires.push_back(w);*/ for (auto b : ctx->getBels()) { if (ctx->getBelType(b) == TYPE_ICESTORM_LC) { - src_wires.push_back(ctx->getWireBelPin(b, PIN_O)); + src_wires.push_back(ctx->getBelPinWire(b, PIN_O)); } if (ctx->getBelType(b) == TYPE_SB_IO) { - src_wires.push_back(ctx->getWireBelPin(b, PIN_D_IN_0)); + src_wires.push_back(ctx->getBelPinWire(b, PIN_D_IN_0)); } } for (auto b : ctx->getBels()) { if (ctx->getBelType(b) == TYPE_ICESTORM_LC) { - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I0)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I1)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I2)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_I3)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_CEN)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_CIN)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I0)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I1)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I2)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_I3)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_CEN)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_CIN)); } if (ctx->getBelType(b) == TYPE_SB_IO) { - dst_wires.push_back(ctx->getWireBelPin(b, PIN_D_OUT_0)); - dst_wires.push_back(ctx->getWireBelPin(b, PIN_OUTPUT_ENABLE)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_D_OUT_0)); + dst_wires.push_back(ctx->getBelPinWire(b, PIN_OUTPUT_ENABLE)); } } -- cgit v1.2.3 From b60c9485d2d324a221c7050aa6437b291b3dedf4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 11:56:51 +0200 Subject: Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 arch Signed-off-by: Clifford Wolf --- ice40/arch.cc | 14 ++++++++++++++ ice40/arch.h | 18 ++++++++++++++++-- ice40/chipdb.py | 29 +++++++++++++++++++++++++++-- 3 files changed, 57 insertions(+), 4 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index a670f286..5f0384a3 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -308,6 +308,20 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const return br; } +PortType Arch::getBelPinType(BelId bel, PortPin pin) const +{ + NPNR_ASSERT(bel != BelId()); + + int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires; + const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get(); + + for (int i = 0; i < num_bel_wires; i++) + if (bel_wires[i].port == pin) + return PortType(bel_wires[i].type); + + return PORT_INOUT; +} + WireId Arch::getBelPinWire(BelId bel, PortPin pin) const { WireId ret; diff --git a/ice40/arch.h b/ice40/arch.h index 566f807a..f3016424 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -46,6 +46,7 @@ template struct RelPtr NPNR_PACKED_STRUCT(struct BelWirePOD { int32_t wire_index; PortPin port; + int32_t type; }); NPNR_PACKED_STRUCT(struct BelInfoPOD { @@ -86,6 +87,9 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD { BelPortPOD bel_uphill; RelPtr bels_downhill; + int32_t num_bel_pins; + RelPtr bel_pins; + int32_t num_segments; RelPtr segments; @@ -466,8 +470,9 @@ struct Arch : BaseCtx } WireId getBelPinWire(BelId bel, PortPin pin) const; + PortType getBelPinType(BelId bel, PortPin pin) const; - BelPin getBelPinUphill(WireId wire) const + BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED { BelPin ret; NPNR_ASSERT(wire != WireId()); @@ -480,7 +485,7 @@ struct Arch : BaseCtx return ret; } - BelPinRange getBelPinsDownhill(WireId wire) const + BelPinRange getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED { BelPinRange range; NPNR_ASSERT(wire != WireId()); @@ -555,6 +560,15 @@ struct Arch : BaseCtx return delay; } + BelPinRange getWireBelPins(WireId wire) const + { + BelPinRange range; + NPNR_ASSERT(wire != WireId()); + range.b.ptr = chip_info->wire_data[wire.index].bel_pins.get(); + range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bel_pins; + return range; + } + WireRange getWires() const { WireRange range; diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 329fef56..6e2bd2b5 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -43,6 +43,7 @@ packages = list() wire_uphill_belport = dict() wire_downhill_belports = dict() +wire_belports = dict() wire_names = dict() wire_names_r = dict() @@ -449,12 +450,18 @@ def add_bel_input(bel, wire, port): if wire not in wire_downhill_belports: wire_downhill_belports[wire] = set() wire_downhill_belports[wire].add((bel, port)) - bel_wires[bel].append((wire, port)) + if wire not in wire_belports: + wire_belports[wire] = set() + wire_belports[wire].add((bel, port)) + bel_wires[bel].append((wire, port, 0)) def add_bel_output(bel, wire, port): assert wire not in wire_uphill_belport wire_uphill_belport[wire] = (bel, port) - bel_wires[bel].append((wire, port)) + if wire not in wire_belports: + wire_belports[wire] = set() + wire_belports[wire].add((bel, port)) + bel_wires[bel].append((wire, port, 1)) def add_bel_lc(x, y, z): bel = len(bel_name) @@ -913,6 +920,7 @@ for bel in range(len(bel_name)): for i in range(len(bel_wires[bel])): bba.u32(bel_wires[bel][i][0], "wire_index") bba.u32(portpins[bel_wires[bel][i][1]], "port") + bba.u32(bel_wires[bel][i][2], "type") index += 1 bba.l("bel_data_%s" % dev_name, "BelInfoPOD") @@ -988,6 +996,15 @@ for wire in range(num_wires): else: num_bels_downhill = 0 + if wire in wire_belports: + num_bel_pins = len(wire_belports[wire]) + bba.l("wire%d_bels" % wire, "BelPortPOD") + for belport in sorted(wire_belports[wire]): + bba.u32(belport[0], "bel_index") + bba.u32(portpins[belport[1]], "port") + else: + num_bel_pins = 0 + info = dict() info["name"] = "X%d/Y%d/%s" % wire_names_r[wire] @@ -1000,6 +1017,9 @@ for wire in range(num_wires): info["num_bels_downhill"] = num_bels_downhill info["list_bels_downhill"] = ("wire%d_downbels" % wire) if num_bels_downhill > 0 else None + info["num_bel_pins"] = num_bel_pins + info["list_bel_pins"] = ("wire%d_bels" % wire) if num_bel_pins > 0 else None + if wire in wire_uphill_belport: info["uphill_bel"] = wire_uphill_belport[wire][0] info["uphill_pin"] = portpins[wire_uphill_belport[wire][1]] @@ -1007,6 +1027,9 @@ for wire in range(num_wires): info["uphill_bel"] = -1 info["uphill_pin"] = 0 + if num_bels_downhill == 0: + info["list_bel_pins"] = None + avg_x, avg_y = 0, 0 if wire in wire_xy: for x, y in wire_xy[wire]: @@ -1085,6 +1108,8 @@ for wire, info in enumerate(wireinfo): bba.u32(info["uphill_bel"], "bel_uphill.bel_index") bba.u32(info["uphill_pin"], "bel_uphill.port") bba.r(info["list_bels_downhill"], "bels_downhill") + bba.u32(info["num_bel_pins"], "num_bel_pins") + bba.r(info["list_bel_pins"], "bel_pins") bba.u32(len(wire_segments[wire]), "num_segments") if len(wire_segments[wire]): bba.r("wire_segments_%d" % wire, "segments") -- cgit v1.2.3 From e13fc7edabb449d21ad6473bab23d5c1b2cf3761 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 22 Jul 2018 12:08:52 +0200 Subject: Add Arch::getBelPins() to generic and iCE40 archs Signed-off-by: Clifford Wolf --- ice40/arch.cc | 15 +++++++++++++++ ice40/arch.h | 2 ++ 2 files changed, 17 insertions(+) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index 5f0384a3..65b21afd 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -340,6 +340,21 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const return ret; } +std::vector Arch::getBelPins(BelId bel) const +{ + std::vector ret; + + NPNR_ASSERT(bel != BelId()); + + int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires; + const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get(); + + for (int i = 0; i < num_bel_wires; i++) + ret.push_back(bel_wires[i].port); + + return ret; +} + // ----------------------------------------------------------------------- WireId Arch::getWireByName(IdString name) const diff --git a/ice40/arch.h b/ice40/arch.h index f3016424..2e2018fb 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -494,6 +494,8 @@ struct Arch : BaseCtx return range; } + std::vector getBelPins(BelId bel) const; + // ------------------------------------------------- WireId getWireByName(IdString name) const; -- cgit v1.2.3 From b9c413a5aa06a325de5c55e254441aee58143676 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sun, 22 Jul 2018 19:58:17 +0200 Subject: Move to new API and remove deprecated --- ice40/arch.h | 23 --------------- ice40/arch_pybindings.cc | 6 ++-- ice40/bitstream.cc | 74 +++++++++++++++++++++++++----------------------- 3 files changed, 40 insertions(+), 63 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.h b/ice40/arch.h index 2e2018fb..3ae6ce65 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -471,29 +471,6 @@ struct Arch : BaseCtx WireId getBelPinWire(BelId bel, PortPin pin) const; PortType getBelPinType(BelId bel, PortPin pin) const; - - BelPin getBelPinUphill(WireId wire) const NPNR_DEPRECATED - { - BelPin ret; - NPNR_ASSERT(wire != WireId()); - - if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) { - ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index; - ret.pin = chip_info->wire_data[wire.index].bel_uphill.port; - } - - return ret; - } - - BelPinRange getBelPinsDownhill(WireId wire) const NPNR_DEPRECATED - { - BelPinRange range; - NPNR_ASSERT(wire != WireId()); - range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get(); - range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill; - return range; - } - std::vector getBelPins(BelId bel) const; // ------------------------------------------------- diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc index a1ce9f5b..246d0f57 100644 --- a/ice40/arch_pybindings.cc +++ b/ice40/arch_pybindings.cc @@ -84,10 +84,8 @@ void arch_wrap_python() fn_wrapper_2a, conv_from_str, conv_from_str>::def_wrap(ctx_cls, "getBelPinWire"); - fn_wrapper_1a, - conv_from_str>::def_wrap(ctx_cls, "getBelPinUphill"); - fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getBelPinsDownhill"); + fn_wrapper_1a, + conv_from_str>::def_wrap(ctx_cls, "getWireBelPins"); fn_wrapper_1a, conv_from_str>::def_wrap(ctx_cls, "getWireChecksum"); diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 9f5d1f66..5559c2ce 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -717,42 +717,44 @@ bool read_asc(Context *ctx, std::istream &in) for (auto w : net.second->wires) { if (w.second.pip == PipId()) { WireId wire = w.first; - BelPin belpin = ctx->getBelPinUphill(wire); - if (ctx->checkBelAvail(belpin.bel)) { - if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) { - std::unique_ptr created = create_ice_cell(ctx, ctx->id("ICESTORM_LC")); - IdString name = created->name; - ctx->cells[name] = std::move(created); - ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); - // TODO: Add port mapping to nets - } - if (ctx->getBelType(belpin.bel) == TYPE_SB_IO) { - std::unique_ptr created = create_ice_cell(ctx, ctx->id("SB_IO")); - IdString name = created->name; - ctx->cells[name] = std::move(created); - ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); - // TODO: Add port mapping to nets - } - if (ctx->getBelType(belpin.bel) == TYPE_SB_GB) { - std::unique_ptr created = create_ice_cell(ctx, ctx->id("SB_GB")); - IdString name = created->name; - ctx->cells[name] = std::move(created); - ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); - // TODO: Add port mapping to nets - } - if (ctx->getBelType(belpin.bel) == TYPE_SB_WARMBOOT) { - std::unique_ptr created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT")); - IdString name = created->name; - ctx->cells[name] = std::move(created); - ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); - // TODO: Add port mapping to nets - } - if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LFOSC) { - std::unique_ptr created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC")); - IdString name = created->name; - ctx->cells[name] = std::move(created); - ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); - // TODO: Add port mapping to nets + for (auto belpin : ctx->getWireBelPins(wire)) { + + if (ctx->checkBelAvail(belpin.bel)) { + if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LC) { + std::unique_ptr created = create_ice_cell(ctx, ctx->id("ICESTORM_LC")); + IdString name = created->name; + ctx->cells[name] = std::move(created); + ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); + // TODO: Add port mapping to nets + } + if (ctx->getBelType(belpin.bel) == TYPE_SB_IO) { + std::unique_ptr created = create_ice_cell(ctx, ctx->id("SB_IO")); + IdString name = created->name; + ctx->cells[name] = std::move(created); + ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); + // TODO: Add port mapping to nets + } + if (ctx->getBelType(belpin.bel) == TYPE_SB_GB) { + std::unique_ptr created = create_ice_cell(ctx, ctx->id("SB_GB")); + IdString name = created->name; + ctx->cells[name] = std::move(created); + ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); + // TODO: Add port mapping to nets + } + if (ctx->getBelType(belpin.bel) == TYPE_SB_WARMBOOT) { + std::unique_ptr created = create_ice_cell(ctx, ctx->id("SB_WARMBOOT")); + IdString name = created->name; + ctx->cells[name] = std::move(created); + ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); + // TODO: Add port mapping to nets + } + if (ctx->getBelType(belpin.bel) == TYPE_ICESTORM_LFOSC) { + std::unique_ptr created = create_ice_cell(ctx, ctx->id("ICESTORM_LFOSC")); + IdString name = created->name; + ctx->cells[name] = std::move(created); + ctx->bindBel(belpin.bel, name, STRENGTH_WEAK); + // TODO: Add port mapping to nets + } } } } -- cgit v1.2.3 From 3788bd26e609f8488ba0f135731a46fb32afa843 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 23 Jul 2018 00:25:49 +0200 Subject: Bugfix in iCE40 chipdb.py Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 3 --- 1 file changed, 3 deletions(-) (limited to 'ice40') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 6e2bd2b5..8cb51e38 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -1027,9 +1027,6 @@ for wire in range(num_wires): info["uphill_bel"] = -1 info["uphill_pin"] = 0 - if num_bels_downhill == 0: - info["list_bel_pins"] = None - avg_x, avg_y = 0, 0 if wire in wire_xy: for x, y in wire_xy[wire]: -- cgit v1.2.3 From 27c523682601e7b504c924a00bec98743fd3477c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 23 Jul 2018 12:19:54 +0200 Subject: Add getGridDimX(), getGridDimY(), getTileDimZ() API Signed-off-by: Clifford Wolf --- ice40/arch.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'ice40') diff --git a/ice40/arch.h b/ice40/arch.h index 3ae6ce65..cd699a0c 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -377,6 +377,12 @@ struct Arch : BaseCtx // ------------------------------------------------- + int getGridDimX() const { return 34; } + int getGridDimY() const { return 34; } + int getTileDimZ(int, int) const { return 8; } + + // ------------------------------------------------- + BelId getBelByName(IdString name) const; IdString getBelName(BelId bel) const -- cgit v1.2.3 From bfa1137fe03a62bf4bcef1d039d520116cc5a13a Mon Sep 17 00:00:00 2001 From: David Shah Date: Mon, 23 Jul 2018 13:02:57 +0200 Subject: clangformat Signed-off-by: David Shah --- ice40/bitstream.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'ice40') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 5559c2ce..9ac8e857 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -482,8 +482,9 @@ void write_asc(const Context *ctx, std::ostream &out) set_config(ti, config.at(y).at(x), "Cascade.IPCON_LC0" + std::to_string(lc_idx) + "_inmux02_5", true); else - set_config(ti, config.at(y).at(x), "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + - "_LC0" + std::to_string(lc_idx) + "_inmux02_5", + set_config(ti, config.at(y).at(x), + "Cascade.MULT" + std::to_string(int(tile - TILE_DSP0)) + "_LC0" + + std::to_string(lc_idx) + "_inmux02_5", true); } } -- cgit v1.2.3 From 90fe002a36a9b90cd6d003d34398242a5d5affb6 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 23 Jul 2018 13:16:27 +0200 Subject: Remove getBelsByType() API Signed-off-by: Clifford Wolf --- ice40/arch.h | 14 -------------- 1 file changed, 14 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.h b/ice40/arch.h index cd699a0c..d4d71cfc 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -439,20 +439,6 @@ struct Arch : BaseCtx return range; } - BelRange getBelsByType(BelType type) const - { - BelRange range; -// FIXME -#if 0 - if (type == "TYPE_A") { - range.b.cursor = bels_type_a_begin; - range.e.cursor = bels_type_a_end; - } - ... -#endif - return range; - } - Loc getBelLocation(BelId bel) const { Loc loc; -- cgit v1.2.3 From e647604e2a584917ad2fc9acfe838a1395c613c2 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 23 Jul 2018 14:03:23 +0200 Subject: Add Context::archcheck() and "nextpnr-ice40 --test" Signed-off-by: Clifford Wolf --- ice40/chipdb.py | 94 +++++++++++++++++++++++++++++++++------------------------ ice40/main.cc | 6 ++++ 2 files changed, 60 insertions(+), 40 deletions(-) (limited to 'ice40') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 8cb51e38..0e8e3ba7 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -373,8 +373,12 @@ with open(args.filename, "r") as f: if line[0] == ".extra_cell": if len(line) >= 5: mode = ("extra_cell", (line[4], int(line[1]), int(line[2]), int(line[3]))) - else: + elif line[3] == "WARMBOOT": + mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 0)) + elif line[3] == "PLL": mode = ("extra_cell", (line[3], int(line[1]), int(line[2]), 3)) + else: + assert 0 extra_cells[mode[1]] = [] continue @@ -564,11 +568,14 @@ def add_bel_ram(x, y): add_bel_input(bel, wire_names[(x, y1, "ram/RCLKE")], "RCLKE") add_bel_input(bel, wire_names[(x, y1, "ram/RE")], "RE") -def add_bel_gb(x, y, g): +def add_bel_gb(xy, x, y, g): + if xy[0] != x or xy[1] != y: + return + bel = len(bel_name) bel_name.append("X%d/Y%d/gb" % (x, y)) bel_type.append("SB_GB") - bel_pos.append((x, y, 0)) + bel_pos.append((x, y, 2)) bel_wires.append(list()) add_bel_input(bel, wire_names[(x, y, "fabout")], "USER_SIGNAL_TO_GLOBAL_BUFFER") @@ -605,51 +612,58 @@ for tile_xy, tile_type in sorted(tiles.items()): if tile_type == "logic": for i in range(8): add_bel_lc(tile_xy[0], tile_xy[1], i) + if tile_type == "io": for i in range(2): add_bel_io(tile_xy[0], tile_xy[1], i) + + if dev_name == "1k": + add_bel_gb(tile_xy, 7, 0, 0) + add_bel_gb(tile_xy, 7, 17, 1) + add_bel_gb(tile_xy, 13, 9, 2) + add_bel_gb(tile_xy, 0, 9, 3) + add_bel_gb(tile_xy, 6, 17, 4) + add_bel_gb(tile_xy, 6, 0, 5) + add_bel_gb(tile_xy, 0, 8, 6) + add_bel_gb(tile_xy, 13, 8, 7) + elif dev_name == "5k": + add_bel_gb(tile_xy, 13, 0, 0) + add_bel_gb(tile_xy, 13, 31, 1) + add_bel_gb(tile_xy, 19, 31, 2) + add_bel_gb(tile_xy, 6, 31, 3) + add_bel_gb(tile_xy, 12, 31, 4) + add_bel_gb(tile_xy, 12, 0, 5) + add_bel_gb(tile_xy, 6, 0, 6) + add_bel_gb(tile_xy, 19, 0, 7) + elif dev_name == "8k": + add_bel_gb(tile_xy, 33, 16, 7) + add_bel_gb(tile_xy, 0, 16, 6) + add_bel_gb(tile_xy, 17, 33, 1) + add_bel_gb(tile_xy, 17, 0, 0) + add_bel_gb(tile_xy, 0, 17, 3) + add_bel_gb(tile_xy, 33, 17, 2) + add_bel_gb(tile_xy, 16, 0, 5) + add_bel_gb(tile_xy, 16, 33, 4) + elif dev_name == "384": + add_bel_gb(tile_xy, 7, 4, 7) + add_bel_gb(tile_xy, 0, 4, 6) + add_bel_gb(tile_xy, 4, 9, 1) + add_bel_gb(tile_xy, 4, 0, 0) + add_bel_gb(tile_xy, 0, 5, 3) + add_bel_gb(tile_xy, 7, 5, 2) + add_bel_gb(tile_xy, 3, 0, 5) + add_bel_gb(tile_xy, 3, 9, 4) + if tile_type == "ramb": add_bel_ram(tile_xy[0], tile_xy[1]) -if dev_name == "1k": - add_bel_gb( 7, 0, 0) - add_bel_gb( 7, 17, 1) - add_bel_gb(13, 9, 2) - add_bel_gb( 0, 9, 3) - add_bel_gb( 6, 17, 4) - add_bel_gb( 6, 0, 5) - add_bel_gb( 0, 8, 6) - add_bel_gb(13, 8, 7) -elif dev_name == "5k": - add_bel_gb(13, 0, 0) - add_bel_gb(13, 31, 1) - add_bel_gb(19, 31, 2) - add_bel_gb( 6, 31, 3) - add_bel_gb(12, 31, 4) - add_bel_gb(12, 0, 5) - add_bel_gb( 6, 0, 6) - add_bel_gb(19, 0, 7) -elif dev_name == "8k": - add_bel_gb(33, 16, 7) - add_bel_gb( 0, 16, 6) - add_bel_gb(17, 33, 1) - add_bel_gb(17, 0, 0) - add_bel_gb( 0, 17, 3) - add_bel_gb(33, 17, 2) - add_bel_gb(16, 0, 5) - add_bel_gb(16, 33, 4) -elif dev_name == "384": - add_bel_gb( 7, 4, 7) - add_bel_gb( 0, 4, 6) - add_bel_gb( 4, 9, 1) - add_bel_gb( 4, 0, 0) - add_bel_gb( 0, 5, 3) - add_bel_gb( 7, 5, 2) - add_bel_gb( 3, 0, 5) - add_bel_gb( 3, 9, 4) + for ec in sorted(extra_cells.keys()): + if ec[1] == tile_xy[0] and ec[2] == tile_xy[1]: + add_bel_ec(ec) for ec in sorted(extra_cells.keys()): - add_bel_ec(ec) + if ec[1] == 0 and ec[2] == 0: + add_bel_ec(ec) class BinaryBlobAssembler: def __init__(self, cname, endianness, nodebug = False): diff --git a/ice40/main.cc b/ice40/main.cc index 24b49184..4de05d00 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -107,6 +107,7 @@ int main(int argc, char *argv[]) options.add_options()("seed", po::value(), "seed value for random number generator"); options.add_options()("version,V", "show version"); options.add_options()("tmfuzz", "run path delay estimate fuzzer"); + options.add_options()("test", "check architecture database integrity"); #ifdef ICE40_HX1K_ONLY options.add_options()("hx1k", "set device type to iCE40HX1K"); #else @@ -315,6 +316,9 @@ int main(int argc, char *argv[]) std::cout << "\n"; } + if (vm.count("test")) + ctx->archcheck(); + if (vm.count("tmfuzz")) { std::vector src_wires, dst_wires; @@ -360,8 +364,10 @@ int main(int argc, char *argv[]) ctx->chip_info->wire_data[dst.index].type); } } + if (vm.count("freq")) ctx->target_freq = vm["freq"].as() * 1e6; + ctx->timing_driven = true; if (vm.count("no-tmdriv")) ctx->timing_driven = false; -- cgit v1.2.3