From 287fe7e89451b952d15c7839aff9cb3db12bf807 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 5 Aug 2018 14:18:34 +0200 Subject: clangformat --- ice40/arch.cc | 66 ++++++++++++++++++++++++++---------------------------- ice40/arch.h | 24 ++++++++++---------- ice40/bitstream.cc | 43 ++++++++++++++++++----------------- ice40/delay.cc | 42 ++++++++++++---------------------- ice40/gfx.cc | 6 +++-- 5 files changed, 84 insertions(+), 97 deletions(-) (limited to 'ice40') diff --git a/ice40/arch.cc b/ice40/arch.cc index de752b59..5d79a487 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -404,38 +404,37 @@ WireId Arch::getWireByName(IdString name) const IdString Arch::getWireType(WireId wire) const { NPNR_ASSERT(wire != WireId()); - switch (chip_info->wire_data[wire.index].type) - { - case WireInfoPOD::WIRE_TYPE_NONE: - return IdString(); - case WireInfoPOD::WIRE_TYPE_GLB2LOCAL: - return id("GLB2LOCAL"); - case WireInfoPOD::WIRE_TYPE_GLB_NETWK: - return id("GLB_NETWK"); - case WireInfoPOD::WIRE_TYPE_LOCAL: - return id("LOCAL"); - case WireInfoPOD::WIRE_TYPE_LUTFF_IN: - return id("LUTFF_IN"); - case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT: - return id("LUTFF_IN_LUT"); - case WireInfoPOD::WIRE_TYPE_LUTFF_LOUT: - return id("LUTFF_LOUT"); - case WireInfoPOD::WIRE_TYPE_LUTFF_OUT: - return id("LUTFF_OUT"); - case WireInfoPOD::WIRE_TYPE_LUTFF_COUT: - return id("LUTFF_COUT"); - case WireInfoPOD::WIRE_TYPE_LUTFF_GLOBAL: - return id("LUTFF_GLOBAL"); - case WireInfoPOD::WIRE_TYPE_CARRY_IN_MUX: - return id("CARRY_IN_MUX"); - case WireInfoPOD::WIRE_TYPE_SP4_V: - return id("SP4_V"); - case WireInfoPOD::WIRE_TYPE_SP4_H: - return id("SP4_H"); - case WireInfoPOD::WIRE_TYPE_SP12_V: - return id("SP12_V"); - case WireInfoPOD::WIRE_TYPE_SP12_H: - return id("SP12_H"); + switch (chip_info->wire_data[wire.index].type) { + case WireInfoPOD::WIRE_TYPE_NONE: + return IdString(); + case WireInfoPOD::WIRE_TYPE_GLB2LOCAL: + return id("GLB2LOCAL"); + case WireInfoPOD::WIRE_TYPE_GLB_NETWK: + return id("GLB_NETWK"); + case WireInfoPOD::WIRE_TYPE_LOCAL: + return id("LOCAL"); + case WireInfoPOD::WIRE_TYPE_LUTFF_IN: + return id("LUTFF_IN"); + case WireInfoPOD::WIRE_TYPE_LUTFF_IN_LUT: + return id("LUTFF_IN_LUT"); + case WireInfoPOD::WIRE_TYPE_LUTFF_LOUT: + return id("LUTFF_LOUT"); + case WireInfoPOD::WIRE_TYPE_LUTFF_OUT: + return id("LUTFF_OUT"); + case WireInfoPOD::WIRE_TYPE_LUTFF_COUT: + return id("LUTFF_COUT"); + case WireInfoPOD::WIRE_TYPE_LUTFF_GLOBAL: + return id("LUTFF_GLOBAL"); + case WireInfoPOD::WIRE_TYPE_CARRY_IN_MUX: + return id("CARRY_IN_MUX"); + case WireInfoPOD::WIRE_TYPE_SP4_V: + return id("SP4_V"); + case WireInfoPOD::WIRE_TYPE_SP4_H: + return id("SP4_H"); + case WireInfoPOD::WIRE_TYPE_SP12_V: + return id("SP12_V"); + case WireInfoPOD::WIRE_TYPE_SP12_H: + return id("SP12_H"); } return IdString(); } @@ -582,8 +581,7 @@ std::vector Arch::getGroups() const group.type = GroupId::TYPE_LOCAL_SW; ret.push_back(group); - if (type == TILE_LOGIC) - { + if (type == TILE_LOGIC) { group.type = GroupId::TYPE_LC0_SW; ret.push_back(group); diff --git a/ice40/arch.h b/ice40/arch.h index ff52c1a5..d3076416 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -90,21 +90,21 @@ NPNR_PACKED_STRUCT(struct WireSegmentPOD { NPNR_PACKED_STRUCT(struct WireInfoPOD { enum WireType : int8_t { - WIRE_TYPE_NONE = 0, - WIRE_TYPE_GLB2LOCAL = 1, - WIRE_TYPE_GLB_NETWK = 2, - WIRE_TYPE_LOCAL = 3, - WIRE_TYPE_LUTFF_IN = 4, + WIRE_TYPE_NONE = 0, + WIRE_TYPE_GLB2LOCAL = 1, + WIRE_TYPE_GLB_NETWK = 2, + WIRE_TYPE_LOCAL = 3, + WIRE_TYPE_LUTFF_IN = 4, WIRE_TYPE_LUTFF_IN_LUT = 5, - WIRE_TYPE_LUTFF_LOUT = 6, - WIRE_TYPE_LUTFF_OUT = 7, - WIRE_TYPE_LUTFF_COUT = 8, + WIRE_TYPE_LUTFF_LOUT = 6, + WIRE_TYPE_LUTFF_OUT = 7, + WIRE_TYPE_LUTFF_COUT = 8, WIRE_TYPE_LUTFF_GLOBAL = 9, WIRE_TYPE_CARRY_IN_MUX = 10, - WIRE_TYPE_SP4_V = 11, - WIRE_TYPE_SP4_H = 12, - WIRE_TYPE_SP12_V = 13, - WIRE_TYPE_SP12_H = 14 + WIRE_TYPE_SP4_V = 11, + WIRE_TYPE_SP4_H = 12, + WIRE_TYPE_SP12_V = 13, + WIRE_TYPE_SP12_H = 14 }; RelPtr name; diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 40bd3e1f..543d7b35 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -230,7 +230,8 @@ static BelPin get_one_bel_pin(const Context *ctx, WireId wire) } // Permute LUT init value given map (LUT input -> ext input) -unsigned permute_lut(unsigned orig_init, const std::unordered_map &input_permute) { +unsigned permute_lut(unsigned orig_init, const std::unordered_map &input_permute) +{ unsigned new_init = 0; for (int i = 0; i < 16; i++) { @@ -381,29 +382,29 @@ void write_asc(const Context *ctx, std::ostream &out) for (int i = 0; i < 4; i++) unused.insert(i); for (int i = 0; i < 4; i++) { - WireId lut_wire = ctx->getBelPinWire(bel, PortPin(PIN_I0+i)); + WireId lut_wire = ctx->getBelPinWire(bel, PortPin(PIN_I0 + i)); for (auto pip : ctx->getPipsUphill(lut_wire)) { if (ctx->getBoundPipNet(pip) != IdString()) { std::string name = ci.wire_data[ctx->getPipSrcWire(pip).index].name.get(); - switch(name.back()) { - case '0': - input_perm[i] = 0; - unused.erase(0); - break; - case '1': - input_perm[i] = 1; - unused.erase(1); - break; - case '2': - input_perm[i] = 2; - unused.erase(2); - break; - case '3': - input_perm[i] = 3; - unused.erase(3); - break; - default: - NPNR_ASSERT_FALSE("failed to determine LUT permutation"); + switch (name.back()) { + case '0': + input_perm[i] = 0; + unused.erase(0); + break; + case '1': + input_perm[i] = 1; + unused.erase(1); + break; + case '2': + input_perm[i] = 2; + unused.erase(2); + break; + case '3': + input_perm[i] = 3; + unused.erase(3); + break; + default: + NPNR_ASSERT_FALSE("failed to determine LUT permutation"); } break; } diff --git a/ice40/delay.cc b/ice40/delay.cc index 7c9b3f29..a9607140 100644 --- a/ice40/delay.cc +++ b/ice40/delay.cc @@ -29,13 +29,11 @@ void ice40DelayFuzzerMain(Context *ctx) { std::vector srcWires, dstWires; - for (int i = 0; i < ctx->chip_info->num_wires; i++) - { + for (int i = 0; i < ctx->chip_info->num_wires; i++) { WireId wire; wire.index = i; - switch (ctx->chip_info->wire_data[i].type) - { + switch (ctx->chip_info->wire_data[i].type) { case WireInfoPOD::WIRE_TYPE_LUTFF_OUT: srcWires.push_back(wire); break; @@ -55,8 +53,7 @@ void ice40DelayFuzzerMain(Context *ctx) int index = 0; int cnt = 0; - while (cnt < NUM_FUZZ_ROUTES) - { + while (cnt < NUM_FUZZ_ROUTES) { if (index >= int(srcWires.size()) || index >= int(dstWires.size())) { index = 0; ctx->shuffle(srcWires); @@ -103,7 +100,8 @@ void ice40DelayFuzzerMain(Context *ctx) namespace { -struct model_params_t { +struct model_params_t +{ int neighbourhood; int model0_offset; @@ -125,26 +123,14 @@ struct model_params_t { static const model_params_t &get(ArchArgs args) { - static const model_params_t model_hx8k = { - 588, 129253, 8658, - 118333, 23915, -73105, 57696, - -86797, 89, 3706, - -316, -575, -158, -296 - }; - - static const model_params_t model_lp8k = { - 867, 206236, 11043, - 191910, 31074, -95972, 75739, - -309793, 30, 11056, - -474, -856, -363, -536 - }; - - static const model_params_t model_up5k = { - 1761, 305798, 16705, - 296830, 24430, -40369, 33038, - -162662, 94, 4705, - -1099, -1761, -418, -838 - }; + static const model_params_t model_hx8k = {588, 129253, 8658, 118333, 23915, -73105, 57696, + -86797, 89, 3706, -316, -575, -158, -296}; + + static const model_params_t model_lp8k = {867, 206236, 11043, 191910, 31074, -95972, 75739, + -309793, 30, 11056, -474, -856, -363, -536}; + + static const model_params_t model_up5k = {1761, 305798, 16705, 296830, 24430, -40369, 33038, + -162662, 94, 4705, -1099, -1761, -418, -838}; if (args.type == ArchArgs::HX1K || args.type == ArchArgs::HX8K) return model_hx8k; @@ -232,7 +218,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const float dx3 = dx2 * dx; float dy3 = dy2 * dy; - float norm3 = powf(dx3 + dy3, 1.0/3.0); + float norm3 = powf(dx3 + dy3, 1.0 / 3.0); // Model #1 float v = p.model1_offset; diff --git a/ice40/gfx.cc b/ice40/gfx.cc index 6eda6913..1ab2fb3c 100644 --- a/ice40/gfx.cc +++ b/ice40/gfx.cc @@ -717,7 +717,8 @@ void gfxTilePip(std::vector &g, int x, int y, GfxTileWireId src, return; } - if (TILE_WIRE_LUTFF_0_IN_0_LUT <= src && src <= TILE_WIRE_LUTFF_7_IN_3_LUT && TILE_WIRE_LUTFF_0_OUT <= dst && dst <= TILE_WIRE_LUTFF_7_OUT) { + if (TILE_WIRE_LUTFF_0_IN_0_LUT <= src && src <= TILE_WIRE_LUTFF_7_IN_3_LUT && TILE_WIRE_LUTFF_0_OUT <= dst && + dst <= TILE_WIRE_LUTFF_7_OUT) { int lut_idx = (src - TILE_WIRE_LUTFF_0_IN_0_LUT) / 4; int in_idx = (src - TILE_WIRE_LUTFF_0_IN_0_LUT) % 4; @@ -732,7 +733,8 @@ void gfxTilePip(std::vector &g, int x, int y, GfxTileWireId src, return; } - if (TILE_WIRE_LUTFF_0_IN_0 <= src && src <= TILE_WIRE_LUTFF_7_IN_3 && TILE_WIRE_LUTFF_0_IN_0_LUT <= dst && dst <= TILE_WIRE_LUTFF_7_IN_3_LUT) { + if (TILE_WIRE_LUTFF_0_IN_0 <= src && src <= TILE_WIRE_LUTFF_7_IN_3 && TILE_WIRE_LUTFF_0_IN_0_LUT <= dst && + dst <= TILE_WIRE_LUTFF_7_IN_3_LUT) { int lut_idx = (src - TILE_WIRE_LUTFF_0_IN_0) / 4; int in_idx = (src - TILE_WIRE_LUTFF_0_IN_0) % 4; int out_idx = (dst - TILE_WIRE_LUTFF_0_IN_0_LUT) % 4; -- cgit v1.2.3