From 02b83d6db6c2d0d690b302459fbe490eaa5d140c Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 10 Jun 2018 15:06:26 +0200 Subject: Debugging on icebreaker --- ice40/bitstream.cc | 28 +++++--- ice40/chipdb.py | 4 +- ice40/icebreaker.v | 187 ++++++++++++++++++++++++++++++++++++++++++++++++++++ ice40/icebreaker.ys | 9 +++ 4 files changed, 217 insertions(+), 11 deletions(-) create mode 100644 ice40/icebreaker.v create mode 100644 ice40/icebreaker.ys (limited to 'ice40') diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 818ba180..9b749717 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -180,10 +180,18 @@ void write_asc(const Design &design, std::ostream &out) IdString())) { input_en = true; } - set_config(ti, config.at(iey).at(iex), - "IoCtrl.IE_" + std::to_string(iez), !input_en); - set_config(ti, config.at(iey).at(iex), - "IoCtrl.REN_" + std::to_string(iez), !pullup); + + if(chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K) { + set_config(ti, config.at(iey).at(iex), + "IoCtrl.IE_" + std::to_string(iez), !input_en); + set_config(ti, config.at(iey).at(iex), + "IoCtrl.REN_" + std::to_string(iez), !pullup); + } else { + set_config(ti, config.at(iey).at(iex), + "IoCtrl.IE_" + std::to_string(iez), input_en); + set_config(ti, config.at(iey).at(iex), + "IoCtrl.REN_" + std::to_string(iez), !pullup); + } } else { assert(false); } @@ -198,10 +206,12 @@ void write_asc(const Design &design, std::ostream &out) int iex, iey, iez; std::tie(iex, iey, iez) = ieren; if (iez != -1) { - set_config(ti, config.at(iey).at(iex), - "IoCtrl.IE_" + std::to_string(iez), true); - set_config(ti, config.at(iey).at(iex), - "IoCtrl.REN_" + std::to_string(iez), false); + if(chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K) { + set_config(ti, config.at(iey).at(iex), + "IoCtrl.IE_" + std::to_string(iez), true); + set_config(ti, config.at(iey).at(iex), + "IoCtrl.REN_" + std::to_string(iez), false); + } } } } @@ -213,7 +223,7 @@ void write_asc(const Design &design, std::ostream &out) for (int x = 0; x < ci.width; x++) { TileType tile = tile_at(chip, x, y); TileInfoPOD &ti = bi.tiles_nonrouting[tile]; - if (tile == TILE_RAMB) { + if ((tile == TILE_RAMB) && (chip.args.type == ChipArgs::LP1K || chip.args.type == ChipArgs::HX1K)) { set_config(ti, config.at(y).at(x), "RamConfig.PowerUp", true); } } diff --git a/ice40/chipdb.py b/ice40/chipdb.py index f6f73d99..1477c78a 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -31,7 +31,7 @@ wire_names_r = dict() wire_xy = dict() num_tile_types = 5 -tile_sizes = {0: (0, 0)} +tile_sizes = {_: (0, 0) for _ in range(num_tile_types)} tile_bits = [[] for _ in range(num_tile_types)] cbit_re = re.compile(r'B(\d+)\[(\d+)\]') @@ -306,7 +306,7 @@ for tile_xy, tile_type in sorted(tiles.items()): print('#include "chip.h"') for bel in range(len(bel_name)): - print("BelWirePOD bel_wires_%d[%d] = {" % (bel, len(bel_wires[bel]))) + print("static BelWirePOD bel_wires_%d[%d] = {" % (bel, len(bel_wires[bel]))) for i in range(len(bel_wires[bel])): print(" {%d, PIN_%s}%s" % (bel_wires[bel][i] + ("," if i+1 < len(bel_wires[bel]) else "",))) print("};") diff --git a/ice40/icebreaker.v b/ice40/icebreaker.v new file mode 100644 index 00000000..fde2c576 --- /dev/null +++ b/ice40/icebreaker.v @@ -0,0 +1,187 @@ +module icebreaker ( + input clk_pin, + input btn1_pin, + input btn2_pin, + input btn3_pin, + output led1_pin, + output led2_pin, + output led3_pin, + output led4_pin, + output led5_pin +); + wire clk, led1, led2, led3, led4, led5, btn1, btn2, btn3; + + (* BEL="18_31_io1" *) //27 + SB_IO #( + .PIN_TYPE(6'b 0110_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) led1_iob ( + .PACKAGE_PIN(led1_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(led1), + .D_OUT_1(), + .D_IN_0(), + .D_IN_1() + ); + + (* BEL="19_31_io1" *) //25 + SB_IO #( + .PIN_TYPE(6'b 0110_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) led2_iob ( + .PACKAGE_PIN(led2_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(led2), + .D_OUT_1(), + .D_IN_0(), + .D_IN_1() + ); + + (* BEL="18_0_io1" *) //21 + SB_IO #( + .PIN_TYPE(6'b 0110_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) led3_iob ( + .PACKAGE_PIN(led3_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(led3), + .D_OUT_1(), + .D_IN_0(), + .D_IN_1() + ); + + (* BEL="19_31_io0" *) //23 + SB_IO #( + .PIN_TYPE(6'b 0110_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) led4_iob ( + .PACKAGE_PIN(led4_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(led4), + .D_OUT_1(), + .D_IN_0(), + .D_IN_1() + ); + + (* BEL="18_31_io0" *) //26 + SB_IO #( + .PIN_TYPE(6'b 0110_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) led5_iob ( + .PACKAGE_PIN(led5_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(led5), + .D_OUT_1(), + .D_IN_0(), + .D_IN_1() + ); + + (* BEL="12_31_io1" *) //35 + SB_IO #( + .PIN_TYPE(6'b 0000_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) clk_iob ( + .PACKAGE_PIN(clk_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(), + .D_OUT_1(), + .D_IN_0(clk), + .D_IN_1() + ); + + (* BEL="19_0_io1" *) //20 + SB_IO #( + .PIN_TYPE(6'b 0000_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) btn1_iob ( + .PACKAGE_PIN(btn1_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(), + .D_OUT_1(), + .D_IN_0(btn1), + .D_IN_1() + ); + + (* BEL="21_0_io1" *) //19 + SB_IO #( + .PIN_TYPE(6'b 0000_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) btn2_iob ( + .PACKAGE_PIN(btn2_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(), + .D_OUT_1(), + .D_IN_0(btn2), + .D_IN_1() + ); + + (* BEL="22_0_io1" *) //18 + SB_IO #( + .PIN_TYPE(6'b 0000_01), + .PULLUP(1'b0), + .NEG_TRIGGER(1'b0) + ) btn3_iob ( + .PACKAGE_PIN(btn3_pin), + .LATCH_INPUT_VALUE(), + .CLOCK_ENABLE(), + .INPUT_CLK(), + .OUTPUT_CLK(), + .OUTPUT_ENABLE(), + .D_OUT_0(), + .D_OUT_1(), + .D_IN_0(btn3), + .D_IN_1() + ); + /*localparam BITS = 5; + localparam LOG2DELAY = 22; + + reg [BITS+LOG2DELAY-1:0] counter = 0; + reg [BITS-1:0] outcnt; + + always @(posedge clk) begin + counter <= counter + 1; + outcnt <= counter >> LOG2DELAY; + end*/ + + assign {led1, led2, led3, led4, led5} = {!btn1, btn2, btn3, btn2, btn1}; +endmodule diff --git a/ice40/icebreaker.ys b/ice40/icebreaker.ys new file mode 100644 index 00000000..7933254d --- /dev/null +++ b/ice40/icebreaker.ys @@ -0,0 +1,9 @@ +read_verilog icebreaker.v +read_verilog -lib +/ice40/cells_sim.v +synth -top icebreaker +abc -lut 4 +techmap -map blinky_map.v +splitnets +opt_clean +stat +write_json icebreaker.json -- cgit v1.2.3