From 95fb0595a591dd68ccb4b39ec0b20738ac047978 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 12 Jun 2018 14:27:04 +0200
Subject: ice40: Debugging and fixing FF configuration
Signed-off-by: David Shah <davey1576@gmail.com>
---
ice40/pack_tests/.gitignore | 2 ++
ice40/pack_tests/ffmodes.v | 8 ++++++--
ice40/pack_tests/test.sh | 14 +++++++-------
3 files changed, 15 insertions(+), 9 deletions(-)
create mode 100644 ice40/pack_tests/.gitignore
(limited to 'ice40/pack_tests')
diff --git a/ice40/pack_tests/.gitignore b/ice40/pack_tests/.gitignore
new file mode 100644
index 00000000..749cb303
--- /dev/null
+++ b/ice40/pack_tests/.gitignore
@@ -0,0 +1,2 @@
+*.vcd
+*_out.v
diff --git a/ice40/pack_tests/ffmodes.v b/ice40/pack_tests/ffmodes.v
index 6ff99bce..c09ced74 100644
--- a/ice40/pack_tests/ffmodes.v
+++ b/ice40/pack_tests/ffmodes.v
@@ -1,6 +1,10 @@
module top(input clk, cen, rst, ina, inb, output reg outa, outb, outc, outd);
reg temp0 = 1'b0, temp1 = 1'b0;
+initial outa = 1'b0;
+initial outb = 1'b0;
+initial outc = 1'b0;
+initial outd = 1'b0;
always @(posedge clk)
if (cen)
@@ -17,8 +21,8 @@ always @(negedge clk)
temp1 <= inb;
-always @(posedge clk or negedge rst)
- if(!rst)
+always @(posedge clk or posedge rst)
+ if(rst)
outa <= 1'b0;
else
outa <= temp0;
diff --git a/ice40/pack_tests/test.sh b/ice40/pack_tests/test.sh
index 24bb6549..7ac3ef76 100755
--- a/ice40/pack_tests/test.sh
+++ b/ice40/pack_tests/test.sh
@@ -5,11 +5,11 @@ yosys -p "synth_ice40 -nocarry -top io_wrapper; write_json ${NAME}.json" $1 io_w
../../nextpnr-ice40 --json ${NAME}.json --pack --asc ${NAME}.asc
icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
-yosys -p "rename top gate\
- read_verilog $1\
- rename top gold\
- hierarchy\
- proc\
- clk2fflogic\
- miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter\
+yosys -p "rename chip gate;\
+ read_verilog $1;\
+ rename top gold;\
+ hierarchy;\
+ proc;\
+ clk2fflogic;\
+ miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\
sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 20 -seq 10 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v
--
cgit v1.2.3