From 7e9209878c81730e6374ff555ea2c52f8d20a0ee Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 3 Aug 2018 15:00:32 +0200 Subject: Reworking packer and placer to use new generic rel legaliser Signed-off-by: David Shah --- ice40/pack.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'ice40/pack.cc') diff --git a/ice40/pack.cc b/ice40/pack.cc index fc182e98..9700bc5d 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -26,6 +26,7 @@ #include "design_utils.h" #include "log.h" #include "util.h" +#include "chains.h" NEXTPNR_NAMESPACE_BEGIN @@ -893,6 +894,8 @@ bool Arch::pack() pack_ram(ctx); pack_special(ctx); ctx->assignArchInfo(); + constrain_chains(ctx); + ctx->assignArchInfo(); log_info("Checksum: 0x%08x\n", ctx->checksum()); return true; } catch (log_execution_error_exception) { -- cgit v1.2.3 From fd2174149c3e4654dbe1571e129fadb312f29c33 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 3 Aug 2018 16:29:44 +0200 Subject: Fixing constraint placement bugs Signed-off-by: David Shah --- ice40/pack.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'ice40/pack.cc') diff --git a/ice40/pack.cc b/ice40/pack.cc index 9700bc5d..e7fdc627 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -23,10 +23,10 @@ #include #include #include "cells.h" +#include "chains.h" #include "design_utils.h" #include "log.h" #include "util.h" -#include "chains.h" NEXTPNR_NAMESPACE_BEGIN @@ -445,7 +445,8 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port) { if (is_clock_port(ctx, port) || is_reset_port(ctx, port) || is_enable_port(ctx, port)) return false; - return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) && port.cell->type != ctx->id("SB_GB"); + return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) && + port.cell->type != ctx->id("SB_GB"); } static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic) -- cgit v1.2.3