From d3f1112580b1920cae8684d95e0c5eb65c785efe Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 10 Jun 2018 17:20:29 +0200 Subject: Improving 5k support Signed-off-by: David Shah --- ice40/chipdb.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'ice40/chipdb.py') diff --git a/ice40/chipdb.py b/ice40/chipdb.py index a756203a..f57d307c 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -220,8 +220,8 @@ def add_bel_io(x, y, z): wire_cen = wire_names[(x, y, "io_global/cen")] wire_iclk = wire_names[(x, y, "io_global/inclk")] - wire_oclk = wire_names[(x, y, "io_global/latch")] - wire_latch = wire_names[(x, y, "io_global/outclk")] + wire_latch = wire_names[(x, y, "io_global/latch")] + wire_oclk = wire_names[(x, y, "io_global/outclk")] wire_din_0 = wire_names[(x, y, "io_%d/D_IN_0" % z)] wire_din_1 = wire_names[(x, y, "io_%d/D_IN_1" % z)] @@ -301,6 +301,15 @@ if dev_name == "1k": add_bel_gb( 6, 0, 5) add_bel_gb( 0, 8, 6) add_bel_gb(13, 8, 7) +elif dev_name == "5k": + add_bel_gb(13, 0, 0) + add_bel_gb(13, 31, 1) + add_bel_gb(19, 31, 2) + add_bel_gb( 6, 31, 3) + add_bel_gb(12, 31, 4) + add_bel_gb(12, 0, 5) + add_bel_gb( 6, 0, 6) + add_bel_gb(19, 0, 7) print('#include "chip.h"') -- cgit v1.2.3